( ESNUG 428 Item 3 ) -------------------------------------------- [04/28/04]
From: Ron Press <ron_press=user domain=mentor spot calm>
Subject: Using FastScan & TestKompress for At-Speed Scan Testing with PLLs
Hi John,
We're seeing a trend to use PLLs for accurate at-speed scan testing, but
many people make it more complicated then it needs to be. Here is a
FastScan and TestKompress trick to take a complicated TAP controller PLL
management and replace it with a much simpler approach.
FastScan and TestKompress support "named" capture procedures to allow users
to define clock generation & control logic as a transform from "external"
cycles to "internal" cycles. ATPG only needs to consider the internal
cycles but tester patterns are saved using the external cycles. The
external cycles often have many more cycles than internal cycles. If ATPG
used external cycles then the processing time for each pattern would be
much longer than possible using internal cycles. When using PLLs for
at-speed scan test, the PLL output clocks are often gated by control logic.
Your PLL control logic needs to be programmable such that a specific PLL
clock sequence can be supplied.
external internal signals
signals (PIs) _____ ___________
| |-----| gating |--- /pll/clk1
reference clk --| PLL | | logic |
|_____|-----|___________|--- /pll/clk2
| | | |
shift clk ----------------' | | |
start_ac_test ------------------' | |
scan_en ---------------------' |
___________ /
control bits -/------| |---'
|___________|
One possible strategy for PLL gating and control logic is to use an AND
gate at each clock output that is gated with a control logic register.
Each 1 value loaded into the register represents a clock pulse enabled
through the gating logic. For example, if the register for /pll/clk1 is
loaded with 0011, then two pulses of /pll/clk1 will be produced at the
PLL /pll/clk1 frequency. Therefore, the "named" capture procedure
internal cycles for this example would just be two cycles of /pll/clk1.
The "external" cycles will require a start_ac_test signal and a method
to load the control bits of the control registers. Two popular
methods exist to load the control register. One is to use primary input
signals that are decoded to control register values. The other technique
is to use a boundary scan TAP controller to load the register. Both of
these techniques work, however, the control register can be initialized
in a much simpler way.
_____ _
| PLL |--------------------------| \____ /pll/clk1
|_____| | ,--|_/
|__ _ _ _ _ | _ _
| |-----|_|_|_|_|---' ________| |_| |_
| | register
start_ac_test ---|___| | external could have many
/ cycles to set up the control
TAP bits \ | register bits.
or |-------/--------'
control PIs /
If primary inputs are used for control bits then they can be loaded within
one external cycle. However, the number of PIs necessary is logarithmic
to the number of test modes. On the other hand, if a TAP controller is
used then no additional IO signals are needed. Even the start_ac_test
signal can come from the TAP. The problem with using a TAP is that many
external cycles are needed for each pattern to initialize the control
register. In addition, if any troubleshooting is necessary then it could
be tricky to work through the TAP state machine.
A simple solution to initializing the control register is to use condition
statements within the "named" capture procedure. The condition statement
allows the user to specify values that must be pre-set by ATPG if FastScan
or TestKompress decides to use the corresponding named capture procedure.
For our example, the control register could be a set of scan cells. The
condition statement would state the necessary values at these scan cell
outputs. As a result, the effort to load appropriate values into the
register is automatically performed by ATPG. No special control PIs or
TAP registers are necessary.
_____ _
| PLL |--------------------------| \____ /pll/clk1
|_____| | ,--|_/
|__ _ _ _ _ |
| |-----|_|_|_|_|---'
| | : : : :......... /pll_clk1_reg/cell0
start_ac_test ---|___| : : : :......... /pll_clk1_reg/cell1
: : :........... /pll_clk1_reg/cell2
no extra PIs or control :............... /pll_clk1_reg/cell3
are necessary
An example of the "named" capture procedure with condition statements:
//****** NAMED CAPTURE PROCEDURE *******
procedure capture clk1 =
// *** have ATPG load internal registers ***
condition /pll_clk1_reg/cell0/q 1;
condition /pll_clk1_reg/cell1/q 1;
condition /pll_clk1_reg/cell2/q 0;
condition /pll_clk1_reg/cell3/q 0;
mode internal =
// internal clock cycles
// launch cycle
cycle =
timeplate tp_launch_clk1_fast; // _______/\_
pulse /pll/clk1;
end;
// capture cycle
cycle =
timeplate tp_cap_clk1_fast; // _/\_
pulse /pll/clk1;
end;
end;
mode external =
//external cycles (what the tester will do)
cycle =
timeplate tp_ext;
force scan_en 0;
force_pi;
force start_ac_test 1;
end;
cycle =
force start_ac_test 0;
end;
cycle =
end;
end;
This is a simple method to control PLLs without using extra IO or a TAP
controller. Named capture procedures can be used even if the PLL and
gating logic isn't available in the design as long as it's behavior is
modeled by the procedures.
- Ron Press
Mentor Graphics Corp. Wilsonville, OR
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