( ESNUG 428 Item 2 ) -------------------------------------------- [04/28/04]
Subject: ( ESNUG 424 #1 ) Beta Presto User Seeing Good VHDL ASIC Results
> I wanted to inform you that I am seeing large runtime improvements and
> memory capacity reductions using a special pre-released version of
> Synopsys Design Compiler -- code named Nighthawk2.
>
> - Philip Jackson
> Conexant Systems, Inc. Newport Beach, CA
From: [ The Knight Who Says "Knee!" ]
Hi, John,
I know you like secret switches. You'll love this one. Anon please.
One of the real pains when going from an FPGA to an ASIC is that Synopsys
DC only takes a small subset of the VHDL code that Synplicity or Exemplar
can take. A fairly large part of the conversion process is the dumbing
down of your VHDL to make it work in Synopsys. I even have some code
commented off with:
-- I hate Synopsys
all through it where our designer had to rewrite things.
Well, Synopsys has finally killed off the old VSS reader for their new
Presto VHDL Compiler. For ASICs, Presto can now deal with almost all of
the VHDL code I've been able to throw at it. Pretty much, if my VHDL will
pass in Exemplar or Synplicity, the new Presto should now synthesize it as
well. Presto still can't infer a RAM, but in ASIC land you need that
control anyway. I've been running Verplex LEC against the output, and had
no problems with the latest release.
The down side is that you need to recompile all of your VHDL code in Presto.
If you have old VHDL libraries that came pre-compiled from the vendor you
can't use them any more. However, recompiling isn't a big deal if you have
VHDL source. Presto is suppose to be out soon. For the current release you
still need a beta license, but it will soon be showing up. To enable it:
hdlin_enable_presto_for_vhdl = true
Synopsys seems to be sitting on this new version of Presto because of all
of the issues found with Presto Verilog when it came out a few years ago,
so I'm not sure when it'll be officially announced.
- [ The Knight Who Says "Knee!" ]
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