( ESNUG 427 Item 10 ) ------------------------------------------- [04/14/04]
From: [ An Anon EDA R&D Engineer ]
Subject: 65 nm Is Going To Be Hell If The Fabs Won't Release The Rules!
Hi, John,
Please keep me anonymous on this!
Recently we have been in discussions with many fabs who are ramping up
into 90 nm, but none of them are willing or able to give us sight of
their design rule manuals. They keep saying things like "130 nm was tough
but 90 nm is worse and has some really obscure design rules" yet won't
show us what they are. Often a customer may think a rule is hard but an
EDA company can see an easy way around it, but ONLY if they know what
the rule is.
The fabs we have engaged with have said that they cannot get us the
rules, even saying that they took 6 months to get the rules released to
Cadence or Synopsys.
This is very damaging application of secrecy. We all know who the
designers will blame when they cannot get designs on new processes to
pass DRC checks at the backend -- that's right the EDA companies. What we
need is just a little more openness, or at least a recognition that the
EDA companies are NOT trying to compete with the fabs and are NOT going
to leak confidential information to other fabs.
It is all very well for a fab to think that it has got an innovative
edge by squeezing another 5 nm off the poly-to-poly spacing, or whatever,
but if the EDA tools cannot support the consequent Byzantine rules then
nobody is the winner.
Just in case any fab type Secret Squirrels are reading this, this is
what a physical EDA company needs to know about a new process:
1) are there any new rules that are unlike the previous generation
(via density rules or end extension rules are recent examples)
2) what is the likely frequency of occurrence of these rules:
a) if they happen once per chip (eg extremely wide metal rules)
then they can be design architected around, and only need a
Calibre etc check
b) if they happen a few times per chip then they need a check
and minimal assistance for manual fixing
c) if they happen a few times a block then they need a check and
an automatic fixing system
d) if they happen every few thousand nets / transistors then the
tool needs to avoid creating the errors, support by a fixing
system
e) if they happen every few nets / transistors then the tool
needs to be redesigned to avoid creating these errors at
all costs
Hence an EDA house needs to know the form of the rules (i.e. what is being
checked, and why) and the numerical values or some approximation to them
to assess the frequency of occurrence -- we do not need the full design
manual just enough to do our job properly!
The pervasive secrecy over these rules within the fabs means that EDA
houses don't really get into their stride of trying to fix new
problems until the designer is too far along design his next product.
For example, he has got all the way through synthesis, floorplan, P&R and
timing closure before his Calibre deck is mature enough to check the
rules, and then he finds a million violations of some new rule!
At this point his project slips by 3-6 months and the design beats up
the EDA supplier!
A lot of this pain could be avoided if fabs recognized that EDA houses
are the guys who make their processes usable. They build the cars, we
build the roads.
It is not just the little EDA guys who have this pain, but the big players,
too. Cadence may have a slightly privileged access to some fabs (because
they do the PDKs for them) but the rest of us have much of the same pain.
And of course remember where much of the innovation in the EDA industry
happens: it is not in the 5000 employee broad spectrum suppliers, but in
the startups which they swallow regularly like vitamin pills.
So come on fab guys, recognize that the EDA houses are on your side and
get you act together -- or 90 nm and 65 nm is going to be very painful.
- [ An Anon EDA R&D Engineer ]
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