( ESNUG 427 Item 1 ) -------------------------------------------- [04/14/04]
Subject: ( ESNUG 426 #1 ) Synplicity vs Xilinx ISE vs Mentor vs Synopsys
> In the past two years, I have probably done ~10 FPGA Verilog Synthesis
> classes and no Leonardo-Exemplar FPGA Synthesis classes. Going back past
> two years, I taught a few Leonardo-Exemplar FPGA synthesis classes but
> the ratio was still probably 20% Leonardo-Exemplar and 80% Synplicity.
>
> I like both tools, but nobody has asked for the Leonardo-Exemplar
> version of the training in at least two years.
>
> - Cliff Cummings
> Sunburst Design, Inc. Beaverton, OR
From: William Lenihan <wlenihan=user domain=raytheon spot calm>
John,
I've been designing FPGAs (98% Xilinx .... xc9500's on up to Virtex-II-Pro)
for 9 years now. When I first got ahold of a synthesis tool -- Synopsys
FPGA Compiler -- I was ecstatic just to finally have one. Then, when I
got a 'free' Synplify license as part of some weird Cadence/Synplicity
grandfathering arrangment of old OrCAD licenses, my work life all of a
sudden seemed like nirvana. I'd never had such a 'step-function' upgrade in
an EDA tool before. Results? Speed of execution? The GUI pseudo-schematic
viewer (HDL Analyst)? Superior on every count. I considered writing to
Sweden to nominate Synplicity for a Nobel prize.
So, I've been happily cruising along with Synplify & Synplify-Pro for 4
years now, trying to champion their cause within my company. That one
node-locked license has now become 5 floating licenses in my department
alone.
Now comes the sad part. Sometime in the last 12-18 months, I started having
problems with Synplify Pro. Seems that every time I upgrade to the latest
version, something that used to work like a champ now causes the tool to
choke. Verilog constructs and/or synthesis pragmas need to modified, added,
or deleted. Sometimes the flaw is in their built-in library files (i.e.,
virtex2p.v). Sometimes they repeat flaws from version to version
(instantiating LVPECL I/O). Whatever happened to Regression Testing? If I
didn't have schedules to meet, I'd kinda enjoy being a Beta tester. But I
do (have schedules), so I can't (enjoy being a Beta tester).
Look, I know that designing & validating EDA software is a tough job. It's
just that Synplicity was so (relatively) flawless for so long, that they
themselves set an exceptional standard. A standard they are currently
falling far short of. I've spoken to my Synplicity Sales and FAE and asked
about whether their recent focus on ASIC synthesis has taken resources away
from the FPGA side of the house. I shouldn't need to tell anyone that they
responded in the negative. John, do you have any insiders who know the real
story of what's gone wrong with Synplicity quality control?
I don't want to rag too much on the tool or the company, because, once it
works, Synplify is still awesome. It's just that I have to waste too much
of my time & put up with too much anxiety to help them get there ...... and
nowadays I gotta go through that every time I need an upgrade. Perhaps it
is time to give Mentor/Exemplar a second look.
- Bill Lenihan
Raytheon
---- ---- ---- ---- ---- ---- ----
From: [ Nobody Expects The Spanish Inquisition! ]
Hi, John,
I must be anon.
While we use FPGAs in our?systems, we also use them for ASIC prototyping;
or for small scale emulation if you like. Our experience has been that
it is not possible to single out one specific tool, which is the best in
every case. Thus we have licenses for all 3 main contenders.
Regarding Mentor, we have had bad experiences with Leonardo, which we have
tried in several occasions - but it has never really managed to get the
attention of the designers in my group. When Precision came along, I tried
it, liked what I saw, and has been promoting it in my group. Today I
believe that Precision and Synplify is used more or less at the same rate.
In December 2003 we did an eval on a specific FPGA design which we needed
to modify for cost reduction, i.e. the design is in a Xilinx Virtex-E 1000
and needed to be ported to a cheaper technology. The results:
Design facts:
Timing: Mostly 39 MHz
One multicycle path is defined (3-cycles)
Pins used: 279
Tri-state buffers: 3736
Block-rams: 50
Special feature is a very large state-machine with more than 1000
CASE/IF/ELSEIF lines to select the next state (This is the multicycle
path). Synplify had a lot of problems with this structure,?as can be
seen in the SLICE use. The evaluation is focused on the amount of
SLICEs used to fit the design, runtime, and the ease of use of the
tool. The number reported is the number reported by ISE 5.2 Place &
Route tool.
?
Xilinx - ISE 5.2
----------------
SLICEs used 75%
The tool has several problems with added/changed complexity of the
design (may crash with fatel error). Largely simple to use and setup.
Newer version 6.1 is to support Linux and Solaris in native mode. On
the PC some of the crash errors has been fixed.
?
Synplicity - Synplify Pro 7.3.1
-------------------------------
SLICEs used 91%
The GUI is simple to use and has good integration with the ISE P&R
part. For several other designs it is known to produce better results
than ISE.
?
Synopsys - FPGA Compiler II 3.8.0
---------------------------------
SLICEs used 68%
The GUI is acceptable, but I would soon prefer the shell. The export
of EDIF netlist and .ncf timing and pin information works fine.
?
Mentor - Precision 2003b.39
---------------------------
SLICEs used 76%
The GUI is very integrated with the ISE P&R tool and will bring
reports in the Precision environment. This seems to be a very robust
tool and work fine in both PC and Unix environment.
Synplify who has a very good name, came out last in our test. Whereas
Xilinx, who is not normally known as having a very good at synthesis?tool,
came in second, only to be beaten by FPGA Compiler II !
As the comments says in the report, the tools from Synplicity and
Mentor are actually rather good. The GUI from FPGA Compiler II could be
better?-- but knowing it is an Synopsys tool, that should not come as a
surprise. :-)
- [ Nobody Expects The Spanish Inquisition! ]
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