( ESNUG 423 Item 14 ) ------------------------------------------- [02/26/04]
Subject: Verification Crisis Questions
I'd ask these guys what technologies they are productizing to automate the
verification process. I want to specify the device verification space
using, say, a functional coverage model and have the toolset do the rest:
generate stimuli, check device response and measure coverage.
That ought to corner 'em!
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What are these guys doing in their companies to both provide the 2X-4X
productivity improvements in their overall CAD flows/products, and to help
grow the corresponding pool of analog designers?
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By the year 2007 we will see design greater than 100 million gate.
1. What is your companies strategy for supporting designs of this magnitude?
2. Does your strategy focus on distributed or parallel processing?
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Looking forward, it seems that chips will eventually be made from building
blocks more complex than gates. Synopsys is clearly reaching in that
direction with DesignWare. Using DesignWare generally gives designers
better results with less effort than creating the equivalent design in RTL.
The problem is that DesignWare locks the designer into a Synopsys flow.
This makes it difficult to build a functionally equivalent FPGA prototype,
perform verification with non-Synopsys tools, or use Cadence, Mentor, Magma,
Synplicity, or Forte tools in a design flow.
What, if anything, are these CEOs' companies doing to create a universally
cross-tool portable set of building blocks that are as universal as the
Verilog language?
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There are two equal but opposite things happening. 1) as an industry we
are streaking toward ever increasing levels of abstraction to deal with
complexity. 2) the rules of physics are being applied ever more
brutally (process variation, OPC, EM, ...)
What are you doing inside of your R&D organizations (structurally) to
bridge the gap between these requirements?
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What is their Verification tool flow difference between SoC design and
Large-complex-Chip design?
What do they see as the difference between SoC and Complex chips?
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There is a lot of confusion about different assertion languages and libs at
the moment:
PSL: Property Specification Language
OVL: Open Verification Library (Verilog modules)
OVA: Open Vera Language
SVA: System Verilog Assertions
SVL: System Verilog assertion Library (SVA version of OVL)
Q: Is the assertion language war a red herring? Assertions are often easy
to write but the real problem is that EDA tools (and engineers) struggle
to formally prove them!
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Is there a future for Verilog? It seems to be ending up as a typical minor
language with limited support and a limited user base. Aren't we better
off climbing on the C bandwagon?
When will system-level design emerge as a major market? It has been talked
about for 10 years now, but no market has yet emerged. What must happen
for system-level design to become significant?
What is the single most important advance we must make to solve the
verification crisis? Or will verification end up taking 150% of
the design time?
What do you see as the most important single tool EDA users need today?
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\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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