( ESNUG 420 Item 4 ) -------------------------------------------- [10/22/03]
From: Stephen O'Connor <syo=user domain=cypress spot calm>
Subject: A Chip Designer Asks What Do Gate-Level Sims Buy You These Days?
Hi John,
We've been looking at what our annotated gate-level sims have in our design
flow and trying to understand the cost/return. We have two extreme views:
i) that every test case should be run against min/max annotated gate
level simulations before tapeout.
ii) that gate simulations are only a poor attempt to model things that
should be covered with static timing analysis and formal verification.
And getting gate level simulations up and running takes work and doesn't
come for free and debugging them can be painful. (I can certainly speak
for Verilog here; I don't know if VHDL eases the burden any.)
So what's the ESNUG users' experience on this? How heavily do you rely on
gate sims? What do they catch that other tools don't? How do they fit into
your design flow?
- Stephen O'Connor
Cypress Semiconductor San Jose, CA
|
|
