( ESNUG 419 Item 5 ) -------------------------------------------- [10/08/03]
Subject: ( ESNUG 412 #13 ) Using Nassda HSIM Along With Cadence Spectre
> In general, for full custom design a foundry has to support the Cadence
> framework. We've tried to go with alternates for full-custom, but it
> just isn't worth it as you are pretty much on your own. There are better
> tools out there for full custom, but Cadence has far better integration.
>
> - Greg Berger
> Primarion, Inc. Tempe, AZ
From: Seema Anand <seema=user domain=broadcom got calm>
Hi John,
I read ESNUG 412 #13, where Greg Berger of Primarion comments on using
Nasssda HSIM with Cadence Spectre. In general, I find HSIM more useful for
final verification of very large chip cores containing a combination of
analog and digital blocks. Most analog blocks are stacked with digital
calibration for currents and caps, so the percentage of analog circuits in
an "analog chip" such as a radio is slowly dropping. You need to simulate
pad to pad with all transistors to establish functionality.
In addition to HSIM, we use behavior modeling for our digital blocks and
Spectre/HSPICE for our analog blocks, then join them with SpectreVerilog.
One issue we have with SpectreVerilog is that the Verilog version used to
design and run the digital blocks is different from the Verilog binary that
SpectreVerilog uses. The current consumption of the blocks cannot be
measured, nor can the interactions with bypass caps, which makes it hard to
catch errors. Unfortunately, the alternative is to let our digital
designers design and simulate the digital sections and the let our analog
guys worry about the analog sections, and just hope that the interface is
what was intended! With the digital and analog blocks so closely embedded
with feedback these days, this sort of approach is very unreliable.
Another way that we use HSIM is for circuits with high frequency components
as well as slow time constant components -- for example, a phase-locked loop
(PLL). Since I know that you like hard data, John: a high frequency VCO in
the gigahertz range needs a time step of 10 psec, whereas a full sim of a
loop lock can take upwards of 50 usec, depending on the loop filter
implemented. It would take 3-4 weeks to simulate using Spectre to see
minimal functionality of the PLL. It might be faster to fabricate the
circuit than to wait for sim results), but that isn't feasible due to the
expense. And if you include digital calibration circuits, the task in
Spectre is unfathomable on a transistor level.
HSIM simulation run results are roughly 50 usec per 24 hrs for a complex
PLL block with 25K elements & 11K simulation nodes. So within 2 days, it
is possible to simulate a full locking cycle as well as a majority of the
calibration all based on a transistor level schematic. It is now possible
to check over a few corners and check the functionality of the calibration
circuit with the actual PLL circuit instead of a behavioral model.
One Nassda negative is that some critical commands are not well documented
and can be understood (or found) only via Nassda's technical support.
Although they are quite helpful, it'd be better to have a well-documented
tool. Unfortunately, a lot of Nassda "do's and don'ts" are discovered only
by trial and error, so it is quite difficult for a novice to take advantage
of their HSIM tool. Some people may be reluctant to use HSIM because of
this obstacle, but once the initial simulation is successful, the advantages
are well worth the effort.
What I like about HSIM are its fast DC convergence capabilities, which is
much faster than Spectre. (This is handy for measuring DC current
consumption of an entire chip and getting reasonable timing information for
power down and power on. These types of simulations are necessary for
catching any misconnected bypass caps that are added late in the design
process.) Another is that with a short script, it is easy to convert the
DC operating point from HSIM into an initial condition file in Spectre and
not have to wait for its DC convergence, which can take up to hours for
very complex circuits.
- Seema Anand
Broadcom Irvine, CA
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