( ESNUG 417 Item 11 ) ------------------------------------------- [09/08/03]
From: Ken Wong <wong=user domain=sd.conexant plot domme>
Subject: One User's First Impressions Of Nassda's Hanex From Its DAC Demo
Hi, John,
I saw a demo of Nassda's Hanex at DAC. I haven't used it yet, this feedback
is only based on the demo that I saw. We do use Nassda's HSIM however.
Hanex uses a hybrid approach that combines both static (cell level) and
dynamic (transistor level) timing to analyze critical paths. Dynamically,
Hanex does clock tree analysis (given the clock source) for improved
accuracy on clock skew, simulates crosstalk effects from backannotated RC
parasitics, and considers voltage dependent capacitance, Miller capacitance,
and nonlinear input slopes for greater accuracy. It reads .lib for
stdcells. But at this writing, Hanex does not yet support sdc constraint
format used by PrimeTime. It's claim to fame is reducing pessimism from
typical cell based STA tools and improving quality of the designs by
incorporating dynamic analysis at the transistor level.
Today my company uses PrimeTime, but I think PrimeTime is starting to run
out of steam because of DSM, eg. noise issues and crosstalk. DSM effects
pull us toward dynamic analysis, yet capacity issues pull us toward static
analysis. We look at hybrid tools to solve this. Hanex is equipped to
look at dynamic effects of those features, in that sense it is suitable,
i.e. from a DAC demo technical standpoint. But from a business standpoint,
we can't just throw away PrimeTime.
We do trust that transistor analysis is more accurate and correlates better,
but don't do it for overall timing analysis because of capacity. The theory
is that Hanex will have the right accuracy with the capacity, but we would
need to evaluate it to verify this. If it diverts from the flow, like Hanex
does, it is okay if you really need to do it.
A Hanex DAC demo vs. PrimeTime comparison:
- PrimeTime relies on characterization of the library, and the
characterization is done in a certain manner, e.g. for a 200 Mhz
speed/frequency. In general, this exact speed is not what the
library is characterized for. Designs may run slower or faster,
and the PrimeTime library is not characterized for that. So you
may not see the same quality with the actual chip.
- PrimeTime is padded (guardbanding) for worst corner and best corner,
where everything all will fall in between. It can't predict nominal
corners.
- Hanex's strong point is that it allows you to not rely on the library,
but instead do actual analysis based on transistor and SPICE model.
Hanex gives a middle point to deal with capacity and acccuracy. So
you are actually doing timing analysis based on true model vs. library.
So you have a better handle on your prediction.
- For Hanex to replace PrimeTime, it needs other capabilities. e.g. it
needs to be able to deal with IR drop.
- When I was at DAC, I asked if Hanex could accept PrimeTime constraint
input, but they said it didn't yet. So Hanex doesn't plug and play
right now, which is important.
Hanex may be easily mistaken for PathMill. But it is a hybrid, so the two
tools are different. Besides, Hanex has other capabilities like SI analysis
that PathMill lacks. Hanex cannot replace PrimeTime, as least not any time
soon. But Hanex may be used to improve the design quality on top of
PrimeTime.
- Ken Wong
Conexant Systems, Inc. San Diego, CA
( ESNUG 417 Networking Section ) -------------------------------- [09/08/03]
Santa Clara, CA -- Mobilygen seeks physical design, verification, & ASIC
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