( ESNUG 417 Item 9 ) -------------------------------------------- [09/08/03]
From: [ Siegfried, not Roy ]
Subject: Two Users Review Mentor's New Precision FPGA Tools vs. Synplicity
Hi, John,
I must be anon.
I had the opportunity to try using Mentor's new Precision RTL on an Altera
Stratix design. The EP1S80 we were targeting was about 90% full according
to Synplify. I tried running through the Precision RTL flow, which I found
quite user friendly. The GUI provides a quick, easy, method to setup a
project. I would compare it on par to the ease of use for Synplify. I
also ran the tool from the CLI, which I found to run faster without the
GUI overhead.
The results out of the run were unfavorable, however. The part was at 103%
utilization, and no matter what constraining and options I set, I could not
get it below that level. Precision provides several clever ways to
constrain a design, ranging from text input in .sdc format, to setting them
graphically in the schematic viewer, as well as in the source code. It was
difficult to see what exactly was causing the area problem, but I would
guess that Precision missed an inference opportunity on a RAM. I have a
good feeling about the GUI and the feature of being able to read in EDIF
files, but as for the algorithm, I think they have some work to do.
In all fairness, however, there is a project that has just started using it
for a Xilinx Virtex design here, and they are seeing great results for both
timing and area. Perhaps Mentor has just had more time to tweak their
algorithm for the Xilinx architecture. I'll definitely keep working with
new revs of the tool to see if Altera performance gets better.
- [ Siegfried, not Roy ]
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From: [ Roy, not Siegfried ]
John, I'm anon.
Recently, I had the opportunity to review Mentor's Precision Physical, while
designing a DSP FPGA for a radio. I was working with a Xilinx Virtex-E 2000
chip, which was using 95% of the LUTs and RAM's on board. The design had
four global clocks, and three DLL's. The chip was designed with a lot of
logic between registers, making it very difficult to make timing.
I had used the Synplify/Amplify flow before, and after 3 months of tedious
manually driven optimization, and declaring several lines "don't care", I
was able to make one version meet timing. The problem was that the results
could not be recreated, and some modifications were going to be required by
the board designers.
After seeing a review of Mentor's Precision Physical, we asked to run this
chip through to test it. After 3 days of configuration work (including
tool installation and testing), the process took 38 minutes in push-button
automatic mode to have a design in which all of the routes made timing.
After making timing, we explored some of the other features. Using color
coding, the software makes it simple to determine where your timing issues
are, and makes it as easy as drag and drop to manually move LUT's and
RAM's around.
Some of the advantages I saw with this software package is an extreme
decrease in the amount of time required to make timing. It also dumps a
complete layout into either Altera's or Xilinx's software. In addition,
it is easier to manually place and see the critical paths.
The biggest drawback I saw was that it's still an iterative process. We
ran Synplify/Amplify, and Xilinx first to get a XDL and DLY file. Since
I already had a netlist I knew could meet timing, we ran those files
through Precision Physical for placement. This mapping was fed back into
Xilinx for final routing. I'm now using a Precision RTL to Physical flow
and am meeting timing constraints. Either way, you still have to
synthesize, place and route, then use Precision Physical to tweak timing,
then place and route again.
Another issue is that there is not an automatic transition from one tool
to another. I needed to set an environment variable to get the Bell Delay
model, and I had to convert the NCD file to XDL.
Over all I was really impressed with the tool. After discovering the
performance of Mentor's Precision Physical, we have incorporated it as
part of our standard tools.
- [ Roy, not Siegfried ]
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