( ESNUG 417 Item 6 ) -------------------------------------------- [09/08/03]
Subject: ( ESNUG 407 #1 ) 0-in, Averant, Real Intent, Jasper, Verplex
> Since the ESUNG readers are always hungry for the dirt, let me give you a
> test case that will break all of these tools.
>
> The design: a UART with built in bit rate generator.
>
> The properties: the data that goes in parallel should come out serially
> in the proper bit order. Add a parity check for good measure. The
> length of all the bits should be the same (i.e. it should not be possible
> to change baud rate while sending a byte.)
>
> This will break each of these verification tools due to the bit rate
> generator causing state explosion. The tools will handle the 10 or so
> states of the shift register, start and stop bits, and parity, but the
> counter feeding that for the bit rate will, in my experience, make each of
> these tools give up and not see the state machine.
>
> - James Lee
> The ASIC Group Fremont, CA
From: James M. Lee <jml=user company=asicgroup plot balm>
Hi, John,
I had see this type of circuit cause problem for static assertion checkers
in the past. After I wrote this I personally contacted:
0-in
Averant Solidify
Real Intent Verix
Tempis Fugit (now Jasper Design)
Verplex
and gave them my UART challenge.
None of these players could successfully do the UART other than 0-in. Only
0-in attempted a UART, but that was only from seeing a hand crafted test
case that Kurt Baty had made for it. (Kurt is on 0-in's Advisory Board, so
he's not exactly unbiased as far as 0-in is concerned.)
My gut sense is that if you want to spend a whole lot of money, 0-in will
help you find more bugs than simulation. I can't rate any of these others
in terms of this UART challenge because they all ran away except 0-in.
- James Lee
The ASIC Group Fremont, CA
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