( ESNUG 417 Item 5 ) -------------------------------------------- [09/08/03]
Subject: ( ESNUG 416 #2 ) Astro Hierarchy Preservation After The Fact
> In one of my last engagements, we resolved an issue with hierarchical
> Verilog using a procedure I think is worth sharing in ESNUG. ...
>
> - Martin Ranke
> Synopsys, Inc. Dresden, Germany
From: Shaojie Xu <shaojie.xu=user company=intel hot gone>
Hi, John,
I think the article of item 2 is very useful. I have a follow up question.
Question to Martin Ranke:
In my layout, which was produced by Apollo/Enterprise (some custom layout
was done), one top level port is missing. I added it into the layout, but
can't update it into logic view (CEL, NETL views).
I tried your method to create a new NETL view by reading in a modified
Verilog file where the new port is added, and did
astInitHierPreservation
astMarkHierAsPreserved
and astDumpHierVerilog.
I can see the new port in the new Verilog file dumped out by Astro, but
when I opened the cell and dump IO, dump TDF, say, I still don't see the
port. Therefore when I do Star-RCXT, the port is missing in the SPEF file.
Could you give me some advice on this?
- Shaojie Xu
Intel Corp Santa Clara, CA
---- ---- ---- ---- ---- ---- ----
From: Martin Ranke <martin.ranke=user domain=synopsys got domme>
Hi Shaoji,
Can You be a bit more specific of how you added the port? My proposal
would be to use the same command Astro uses itself to create the port.
If you dump the floorplan and deselct everything except Dump IO Cells,
you will have in the floorplan dump file the syntax requires to create a
pin. I think the command is something like dbRecreatePin, but check the
dump to be sure, I currently can not access an Astro session to double
check.
There is also an online help to the command in question.
After you have recreated the pin I would expect it to show up also in
the IO TDF.
Let me know if this works.
- Martin Ranke
Synopsys, Inc. Dresden, Germany
|
|
