( ESNUG 416 Item 2 ) -------------------------------------------- [07/30/03]
From: Martin Ranke <martin.ranke=user domain=synopsys spot calm>
Subject: How To Initialize Astro Hierarchy Preservation After The Fact
Hi John,
My name is Martin Ranke. I am physical design specialist working for
Synopsys in Germany. These days I am predominantly focused on working with
customers converting from Apollo and doing their first tapeouts in Astro.
In one of my last engagements, we resolved an issue with hierarchical
Verilog using a procedure I think is worth sharing in your ESNUG forum.
Bear with me, the details are a bit involved:
I think most long term users of Apollo are well familiar with the inherent
problems of its hierarchical Verilog out procedure. Just as a quick recap:
The fundamental problem is that Apollo flattens out the netlist right after
reading it in. All changes to the netlist in Apollo are done on this flat
netlist. When the user is ready to write out a hierarchical netlist, they
have to create HNET views. This process regenerates the hierarchy by
looking at the net & cell names in the layout and taking a very complicated
educated guess how the hierarchy needs to look like.
In Astro, this process is eliminated by the new hierarchy preservation
mechanism. Astro has a separate process running concurrently to your layout
activities to maintain the netlist hierarchy. Any command changing the
netlist will inform this mechanism and the hierarchy is always up to date.
You get a netlist with just pushing a button.
However, in order for this to work you need to call two commands before you
start changing the netlist in the layout.
astInitHierPreservation
astMarkHierAsPreserved
Side Note: This also replaces the cmCreateHierPorts command from Apollo.
Calling these commands establishes a link between the flat view of the
layout connectivity in the CEL view to the initial hierarchical connectivity
in the Verilog NETL view.
To make the Astro hierarchical Verilog work you need to run the above two
commands while the CEL view and NETL view are still in sync. This is BEFORE
any netlist changes. This is the user's responsibility and does not occur
automatically.
In the case of my customer, they had started design without being aware of
this change in the Astro flow vs. Apollo. He had already completed 8 blocks
and was ready to generate a hierarchical Verilog netlist. He did not have
the time or intention to go back to the start of the flow.
We tried to used the old Apollo based HNET flow that is still accessible
inside Astro using the same commands as Apollo. Unfortunately the netlist
was not able to back annotate very well, i.e. there were ~1000 unannotated
nets on a block of 60000 nets, due to some name matching problems caused
by the HNET view generation.
The customer needed a means to initialize the Astro hierarchy preservation
after the layout was finished. Here is the process we used to solve this
problem:
1) Read back the netlist we got from the HNET flow, possibly with
some manual or script based changes to get the names to look as
we need them.
2) Do an ECOByNetCompare with this netlist to our layout. (For the
non-daily Astro/Apollo users, the ECOByNetCompare is a command in
Astro/Apollo that reads a flattened netlist and compares all cells,
connections, and net names to the current layout. Updates are then
made to the current layout to bring it into sync with the flattened
netlist.) In this scenario, the ECO will not change any connectivity
but it will change the net names in the layout (CEL view) to match
the net names from the newly read netlist (NETL views). This
resolves the name matching problems and eliminates the unannotated
nets mentioned above.
3) Since the CEL view is now in sync with the NETL views we can
initialize the hierarchy preservation using the two Astro commands
above. From this point on Astro is able to use the astDumpHierVerilog
command that writes the netlist correctly and in just a few seconds.
Now the names from the netlist match the layout and the back annotation
has zero errors.
This procedure can also be used to convert legacy blocks done in Apollo to
Astro and write out hierarchical netlist using the Astro astDumpHierVerilog
command.
I think most Astro customers today are well aware of the changed flow in
Astro to utilize its concurrent hierarchical Verilog Out mechanism. But
for those who still need to work with layout data created without hierarchy
preservation the procedure I suggest in this post might be a welcome help.
- Martin Ranke
Synopsys, Inc. Dresden, Germany
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