( ESNUG 415 Item 1 ) -------------------------------------------- [07/16/03]
Subject: ( ESNUG 409 #7 ) A Denali vs. DW Mem Controller Bake Off (Part I)
> Before your readers go off and waste their time and money on Denali IP,
> I suggest they have a look at what they already own as part of the
> DesignWare library... The DesignWare Memory Controller is fully silicon
> proven. It comes with a full verification environment so it is easy to
> verify your chosen configuration. As you own the DesignWare Library, you
> are already licensed to use the memory controller at no extra cost to
> your company. You can use this component in as many designs as you like,
> royalty free.
>
> - Mick Posner
> Synopsys
From: John Cooley <jcooley@theworld.com>
Hi, All,
Within 12 hours of Mick Posner's letter being published in ESNUG 409 #7,
I got a long and angry response back from Kevin Silver, VP of Marketing
at Denali. It contained the expected blast against Mick plus a boast:
Regarding Mr. Poser's comment about customers "wasting time and money",
I think he should show a little more respect. I'm pretty sure that the
ASIC designers in ESNUG are quite competent to recognize a quality
memory product from yet another "DesignWare throw-in".
Over 35 semiconductor companies are using Databahn memory controllers IP
in their chip designs. We have a 100% first-pass silicon success rate,
with 17 DDR controllers in silicon.
- Kevin Silver, VP Marketing
Denali Austin, TX
The blast back is OK. But I usually don't let EDA vendors make technical
boasts in ESNUG that are unprovable. I phoned Kevin.
Me: "Hey, Kevin, I see you're bragging about 17 DDR controllers in
silicon. Can you back this claim?"
Kevin: "Yes! Our customers love it! Blah-blah-blah! Blah-blah-blah!
Blah-blah-blah-Blah-blah-blah-Blah-blah-blah-Blah-blah-blah..."
Me: "I heard you say yes. Cool. So either you give me the customer
names who can back your claim or I'll be writing a column about
your empty public boasting. You choose. I'll also approach the
Synopsys DW mem people on this with the exact same requirement.
It'll be fun to see what's the actual truth here."
Kevin: "Oh. ... Can I have 2 days to think this over?"
Me: "You have 2 hours." (I didn't want to give him time to rig this.)
Within 24 hours Kevin sent me a list of 41 Denali Databahn users. I sent
all 41 of those users a survey and 24 (58%) replied back with details.
What I found was only 22 different companies using Denali's Databahn
controller -- NOT the 35 Kevin claimed. There were only 9 total Denali
"DDR controllers in silicon", NOT the 17 Kevin claimed. (And 3 of
those 9 "DDR controllers in silicon" occured in one company: Corrent.)
So Kevin's claims were off only by 37 to 47 percent. But, hey, this isn't
the first time that I've caught an EDA marketing person exaggerating the
so-called "facts" in an attempt to sell more of his or her wares! :)
Enclosed are the detailed Denali user responses. Public spankings aside,
that's where the interesting tech story is here, though. In a later ESNUG
I'll send you the Synopsys DW mem IP user responses to the same questions.
- John Cooley
the ESNUG guy
---- ---- ---- ---- ---- ---- ----
> What type of memory are you using? What speed is your memory running at?
> What is your data path width? What process are you designing for?
DDR FCRAM, 155 MHz. We have two different apps on chip. One is 48 bits,
the other 32 bits. TSMC 0.13 um
- Bill Sullivan of Agere Systems
FCRAM, 200 MHz, 72 bits (64 bits + 8 ECC). NEC 0.13um.
- Joe Coyne of Infinicon Systems
DDR-SDRAM, 125 MHz, 32-bits. TSMC 0.13
- Qasim Shami of LSI Logic
DDR ~130MHz 32 0.13
- Helena Zheng of 3DSP
DDR-I SDRAM, 125 MHz, 32-bits. TSMC 0.13 um
- [ An Anon Engineer ]
DDR-SDRAM 133 MHz On the current chip, it's 32 bits. On previous chips,
it was 64 bits. UMC 0.15
- Vaughn Langston of Corrent Corp.
DDR-SDRAM, Data rate: 400MHz (clock 200MHz), 64 bit. 0.13 um
- Takuro Takahashi of NTT Electronics Corp.
We used RLDRAM, the Infineon HYB18RL25632AC-5 devices, in an FPGA. The
memory devices run at 200MHz, the FPGA at 200MHz as well (400MHz DDR),
64 bit wide memory, 8M deep using 2 devices. We designed for the Xilinx
Virtex-2 FPGA family. Check with Xilinx for process.
- Warren Miller of Avnet
DDR-SDRAM, 167 MHz, 32 bit at the memory interface; can be set also to 16 by
writing into a configuration register. Infineon 0.13 um
- Frank Pitter of Infineon
FCRAM, 100 MHz, 32-bit, Xilinx FPGA, Virtex-II
- [ An Anon Engineer ]
DDR, 167 Mhz, 64-bits. TSMC 0.13 um
- Majid Shushtarian of Quicksilver Technology
DDR-SDRAM, upto 200 MHz, 64 bits data with 8 bit ECC. Toshiba 0.13 um
- Abhijeet Ghadje of Netcontinuum
RLDRAM II, 400 Mhz DDR, 32-bits external /128-bits internal. Toshiba 0.13
- Bill Sexton of Texas Instruments
We focus on AHB SDR/DDR controllers limited to 167 MHz.
- Wiegert Wiertsema of Philips Semiconductors
DDR-SDRAM, 300MHz, 128-bits, TSMC .15u and UMC .13u.
- Brad Howe of Altera
RLDRAM II, 800 MHz, 64-bit. Toshiba 0.13 um
- Barry Katz of Signal Integrity Software, Inc.
DDR-SDRAM. 100, 120, 167 & 200 MHz. 32, 64 bits. Both UMC's & TSMC's
0.18u standard CMOS process
- Hugh Chow of ViXS Systems
DDR-SDRAM, Compact Flash, Nand Flash. 150 MHz, 64 bits, LSI GFlx (0.11um)
- WeeHow Lim of Hewlett-Packard
DDR-SDRAM & Flash, 133 MHz, 64 bit, 0.13 um
- [ An Anon Engineer ]
DDR I & II, 167+ MHz, 128 bits. 0.13 um (vendor not specified at this time)
- Phil Lowe of Azul Systems
DDR-SDRAM. Supporting full range between 100 - 167 Mhz. We have in
principal 64 bit of data + 8 bit of ECC. We have a built in option to have
a half width I/F for low performance systems, which means 32 bit + 8 bit of
ECC. This is an integral part of the controller that we were able to
explain the advantages to Denali and got implemented. We have their
controller in two process libraries, both IBM ASIC. SA27E & CU11
- Dror Har-Chen of Silverback Systems
DDR-SDRAM, 200 Mhz - 266 Mhz, 64 bits. Toshiba 0.13 um
- Andy Le of Toshiba
DDR-SDRAM, 200 MHz, 64-bits + 8-bit ECC. We used TSMC 0.15 um. The next
design is for TSMC 0.13 um.
- Bidyut Parruck of Azanda
DDR-SDRAM. One controller will run at 166 MHz and the other at 200 MHz.
The 166 MHz controller will have a 16 bit data path and the 200 MHz
controller will have a 32 bit data path. TSMC 0.13um G. We're actually
incorporating two separate Denali DRAM controllers into our chip.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> What memory devices are supported? (i.e. up to N micron 256M x 16 devices)
5 x 256M FCRAM
- Bill Sullivan of Agere Systems
9 Fujitsu & Toshiba FCRAM parts (8Mx8)
- Joe Coyne of Infinicon Systems
2 128M x16 devices or 1 128 x32 device. We support DDR266 speed parts.
- [ An Anon Engineer ]
When you order a controller from Denali, the Databahn interface gives you a
long list of parts that are compatible with your controller configuration.
We expect that our customers will probably use 32-bit wide parts, or maybe
even 16-bit. We can support a total of 256 MB, but that requires using
8-bit wide parts, given what's available now.
- Vaughn Langston of Corrent Corp.
Memory devices with its address width: 13 bit, data width: 64 bit, and
CAS Latency: 3.
i.e.: 128Mbit(4banks x 1Mword x 32bit with 1DQS) x 2
128Mbit(4banks x 1Mword x 32bit with 4DQS) x 2
128Mbit(4banks x 1Mword x 32bit with 1DQS) x 4
128Mbit(4banks x 1Mword x 32bit with 4DQS) x 4
128Mbit(4banks x 2Mword x 16bit with 1DQS) x 4
128Mbit(4banks x 2Mword x 16bit with 2DQS) x 4
256Mbit(4banks x 2Mword x 32bit with 4DQS) x 2
256Mbit(4banks x 2Mword x 32bit with 4DQS) x 4
etc.
- Takuro Takahashi of NTT Electronics Corp.
Two devices, 8M by 32-bits each for a Xilinx FPGA.
- Warren Miller of Avnet
x18
- Barry Katz of Signal Integrity Software, Inc.
Up to 20 256M x 8 devices from several vendors
- Frank Pitter of Infineon
We will be mainly using DDR-SDRAM DIMMs ranging from 256 MB to 2 GB up to a
maximum of 2 DIMMs. Dual and Quad stacked DIMMs are also supported.
- Abhijeet Ghadje of Netcontinuum
Toshiba and Samsung 256M x 16
- [ An Anon Engineer ]
256 Mbit & 512 Mbit devices
- Bill Sexton of Texas Instruments
Up to 4 devices, no specific vendor.
- Brad Howe of Altera
128 Mb up to 512 Mb, x16 or x32
- Hugh Chow of ViXS Systems
128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit for x8,x16,x32 parts
- WeeHow Lim of Hewlett-Packard
We'll be using DIMM's, so Micron, Samsung 1GB DIMM modules.
- Phil Lowe of Azul Systems
Not sure if you're asking about the load (number of devices) or the depth of
the devices... We have (on 1 of the chips) duplicate control lines. This
is nothing to do with the controller, its our own duplication. This allows
of up to 4 banks with 5 component is a bank, meaning 4 loads on data/strobe,
and 10 (4x5/2) loads on control, 5 loads on chip select.
On the second chip we are maxing it to 2 banks.
If you wanted to know device types then here is a sample -
x8 : 128Mb, 256Mb, 512Mb
x16 : 128Mb, 256Mb, 512Mb
x32 : 64Mb, 128Mb, 256Mb
- Dror Har-Chen of Silverback Systems
256MB X 8
512MB X 4
- Andy Le of Toshiba
Up to three banks of x32 devices.
- Bidyut Parruck of Azanda
For the x16 controller, we will interface to a single x16 device. Supported
devices will be in the range from 128Mbit to 1Gbit. Our goal is to support
all DDR333 devices from Micron, Samsung, Hynix, Elpida, and Infineon that
meet those criteria. For the x32 controller, we will interface to a single
x32 device. Supported devices will be 128 Mbit, 256 Mbit, and 512 Mbit.
Currently, only Micron and Hynix are offerring x32 devices, but we will
attempt to support devices from any vendor that provides a datasheet in the
right timeframe for our development.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did the Denali controller meet your performance requirements? Was it
> optimal for your application?
Yes and yes.
- Bill Sullivan of Agere Systems
It does meet our performance, we have not tuned it yet to decide if we can
improve on the performance.
- Qasim Shami of LSI Logic
Yes. It had some difficulty handling the data patterns in an optimal
manner, but Denali provided a timely update to address the deficiency.
- [ An Anon Engineer ]
The design itself easily meets our performance requirements. The real key
to meeting performance, however, lies in the layout. Denali has made a number
of improvements in the latest release of their DDR controller to alleviate
layout problems we encountered on previous chips.
- Vaughn Langston of Corrent Corp.
Yes, Denali controller met our performance requirements and it was optimal
to our application.
- Takuro Takahashi of NTT Electronics Corp.
We used the DataBahn memory controller generator and dialed the features for
our FPGA design. We were able to easily select the features we needed and
left out the ones that were not important to save FPGA space and to hit our
speed requirement.
Speed was a challenge to hit, but Denali helped us determine the right
approach for the 400 MHz data rate and small capture window provided by the
devices. Internal performance was easier to hit -- it was just a matter of
selecting the right set of functions and Denali helped us with that, too.
- Warren Miller of Avnet
Yes it does.
- Frank Pitter of Infineon
Absolutely. We are working on a 800mbs RLDRAM II controller from Denali.
Specifically focusing on the critical timing paths through key logic paths
through the controller and system level loop timing.
- Barry Katz of Signal Integrity Software, Inc.
Our requirement was to operate at 125 MHz. Denali was very clear & told us
that in FPGA their controller can not go faster than 107 MHz. When Denali
delivered their code, we could synthesize their code and the timing report
showed that their controller could run at 117 MHz. Nice surprise.
- [ An Anon Engineer ]
We have not undergone a performance analysis yet.
- Abhijeet Ghadje of Netcontinuum
Yes/Yes
- Bill Sexton of Texas Instruments
Yes, but I would not call it optimal for my applications.
- Brad Howe of Altera
Denali's controller is a bit too universal. Without a few of the unused
features, the controller could have probably been more efficient or
synthesized to a higher speed to provide more bandwidth. Currently, to
support some of the configuration at higher speed, we have to do quite a
bit of optimization internally. We do have our in-house expertise.
- Hugh Chow of ViXS Systems
It is good and Denali can support whatever customer requested. The only
problem is the delivery is not very timely.
- WeeHow Lim of Hewlett-Packard
It did meet our performance requirements with much work on the backend.
Denali did not have very good support. Since then they have assured us
that the support is much better.
- [ An Anon Engineer ]
Yes, it does. The part where it wins over others is the rich set of
configurability for various datapath widths, row/column mixing, and other
features such as programmble auto vs. self-refresh. The intention of this
design is for higher speed such as DDR333 or above type of application.
- Phil Lowe of Azul Systems
Io put it simple - IT DID, AND IS!!! More words? Well, first of all for
us not having the DRAM I/F working would have been a disaster, being a
startup and tapeout costs only rising (as the process shrinks ;-) - we
stressed that to Denali since day 1, and they worked to show us they really
are doing everything possible that it will work.
It works great, supporting all the configuration it was supposed, too.
- Dror Har-Chen of Silverback Systems
Yes
- Andy Le of Toshiba
Yes.
- Bidyut Parruck of Azanda
Denali has worked with us to customize the internal I/F to their controller
for the specific requirements of our chip. This has been very helpful in
optimizing the performance and easing timing issues.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did the Denali controller support your synthesis/simulation/STA flow?
Synthesis - Denali really wanted us to synthesize the Databahn block
standalone and then just pull it in as a .db at the top level. Our
DC guru wanted an overall flow for every block in the chip and wasn't
crazy about special casing Denali. It took quite a bit of work
to port Denali's constraints into our Design Compiler flow.
Simulation - I thought this block was pretty difficult to integrate into
our simulation environment. It's very sensitive to # delays along the
read/write data and strobe paths. This was all done very nicely in their
standalone test bench, but moving those delays to our full chip when I
instantiated the block was a bear. Miss a `timescale somewhere and you
pull your hair out until you realize your 0.5ns delay is actually 0.05ns.
My number one request from Denali would be some sort of RTL sim mode which
does not require # delays anywhere. Would have saved me a lot of time
integrating the block.
STA - Don't have layout parasitic info yet, so no data on this.
- Bill Sullivan of Agere Systems
We are just entering this phase. Dont have actual data yet, we just started
the first synthesis run today!
- Qasim Shami of LSI Logic
Yes.
- Helena Zheng of 3DSP
Yes. PrimeTime scripts could be improved. We just learned that Denali has
already redesigned them. (We have not had time to review the new scripts).
- [ An Anon Engineer ]
Denali includes Design Compiler and PrimeTime scripts with their controller.
I started with their synthesis scripts and integrated them into our DC flow,
and this was fairly painless. We're currently analyzing timing on our
first pass of the layout using a combination of their scripts and ones we
developed from the previous chips.
- Vaughn Langston of Corrent Corp.
Yes, Denali controller supported our environment for synthesis (Design
Compiler), simulation (VCS) and STA (PrimeTime).
- Takuro Takahashi of NTT Electronics Corp.
We used Synopsys FPGA Express for synthesis and ModelTech Modelsim for
verification. The Denali RTL fit right into our desired flow.
- Warren Miller of Avnet
Yes it does.
- Frank Pitter of Infineon
Yes
- Majid Shushtarian of Quicksilver Technology
Yes.
- Brad Howe of Altera
Yes, though synthesis gave us some headaches.
- Hugh Chow of ViXS Systems
It support synthesis and simulation only. For STA, I haven't got any
support yet.
- WeeHow Lim of Hewlett-Packard
Yes, in most cases. It supported VCS, NC-Verilog , as well as MTI which
covers most cases.
- Phil Lowe of Azul Systems
Yes, we're using Buildgates, and I guess Denali does to date because of us.
Sim is NC-Verilog (you can see our frontend is Cadence) - no problem there.
Since we are working with IBM, Denali assigned a person to work with us on
translating the prime time constraint into Einstimer. The nice thing with
Einstimer (I feel awkward saying there is such a thing) is that once you
know what they intend, you can define very strong user defined tests, and
the IBM tool crack the ugly I/F timing for you - it just depends on the
quality of the assertions.
- Dror Har-Chen of Silverback Systems
Yes. Completed synthesis/STA scripts were provided, as well as all
simulation models.
- Andy Le of Toshiba
Yes.
- Bidyut Parruck of Azanda
Yes. We are completely Cadence for our simulation and synthesis tools
and Denali was one of the few IP vendors that provide BuildGates
synthesis scripts.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Which P&R tool do you use? Did it have any troubles with the controller?
> What RC extraction and DRC/LVS tools did you use? Did they have any
> troubles with the Denali controller? Which DFT tools did you use? Find
> any mem controller issues?
Block is still in the early stages of layout. Haven't heard any feedback
about issues from the physical designers. Just lots of questions about nets
that need to be hand routed, where to place certain blocks, etc.
LogicVision for DFT. We had several problems. Until very recently, Denali
hasn't supported LogicVision. We had to ask for a few tweaks in their RTL
(mostly having to do with the handling of async resets within the block) in
order to get LV to run properly.
- Bill Sullivan of Agere Systems
Magma tool suite. Too early to discuss issues. We are in early stage of
physical design, so many questions can't yet be answered.
- Joe Coyne of Infinicon Systems
Magma. None that I know of.
- Barry Katz of Signal Integrity Software, Inc.
Avanti. No troubles. Star RC. No troubles.
- Helena Zheng of 3DSP
Apollo. The controller had no timing issues. Some parts required manual
layout, but that work was planned (e.g. delay line). Calibre, no problem.
Mentor DFT Advisor. The delay line structure is not tested.
- [ An Anon Engineer ]
We use a combination of Synopsys PhysOpt and Apollo. Star-RXCT for
extraction and Hercules DRC/LVS. TetraMax.
- Vaughn Langston of Corrent Corp.
We are told from our ASIC foundry that they used Cadence Silicon Ensemble.
(ASIC foundry did all P&R.) We did not have any troubles with Denali
controller. As Denali controller is not a hard-macro IP and our ASIC
foundry used a commercially available P&R tool, we paid attention to the
even-length signal wiring and floorplanning of the memory controller block.
In addition, we recently heard that the latest version of Databahn does not
require to route the signals evenly as long as one DQS signal is assigned
for each bite, that will reduce the restriction of P&R tool.
We heard that our ASIC foundry used Test Compiler, TetraMax, BSD Compiler.
(ASIC foundry did all DFT.) We did not have any problems with Databahn.
- Takuro Takahashi of NTT Electronics Corp.
We used Xilinx ISE 4.2 for place and route. No troubles, but timing budget
was tight on the memory interface so some time was spect on optimizing the
data capture logic portion of the design. FPGA Design -- no DFT required.
- Warren Miller of Avnet
We ran the controller through Magma BlastFusion without any severe problems.
We were using StarRC and Assura without any problems. We used DFT Advisor
from Mentor and found one problem in the design that has been fixed quite
fast by Denali.
- Frank Pitter of Infineon
Work in progress
- Majid Shushtarian of Quicksilver Technology
We have not yet started any of our back end work. However, the first
pass synthesis looks fine. We did start with our simulations and we
did not face any problems yet.
- Abhijeet Ghadje of Netcontinuum
Have not taken delivery as of yet.
- Bill Sexton of Texas Instruments
Cadence SE. No issues.
Mentor Calibre. No issues.
Mentor DFT. No issues.
- Brad Howe of Altera
Version 5.1 of Xilinx PAR. Tool had no trouble to operate at 117 MHz.
- [ An Anon Engineer ]
Cadence SE & SOC. We had to make adjustments to some of the logic for
improved results. Combined Cadence & Mentor for RC. Most problems were
manageable. Mentor for DFT. However, pad interface logic could not be
scan-inserted.
- Hugh Chow of ViXS Systems
Backend is done by LSI Logic.
- WeeHow Lim of Hewlett-Packard
No, there is nothing hard set in the IP except for the Soft DLL which
needed some physical design and SPICE analysis. We're still in the process
of picking P&R tools at this time.
No, since it is a soft IP, it does not affect DRC/LVS.
We will be inserting full scan. Attention should be placed on how
observable the DLL chain is.
- Phil Lowe of Azul Systems
IBM tools. First chip was with the suite of tools from Bonn University.
Second chip with IBM PDS tools. In the first chip we used the IBM hardened
DLL to lower the risk (although it lowers flexibility as it is 90 degree
only). Second chip we are using the Denali discrete implementation.
IBM methodology include some concepts to ease I/O timing. (BTW - when
evaluating COT flow for the future I saw none of tools in the market really
look at this as seriously) and these helped also to close timing on the
delicate data/strobe relationship.
IBM tools didn't seem to have a problem with anything.
Again - IBM testbench tools - LSSD. Denali have a "prospect" test logic MUX
in many places in RTL already. We instructed synthesis to treat these as
being always in non-test mode, and integrated the controller to be always in
functional mode. From there IBM inserted LSSD test and nothing broke.
- Dror Har-Chen of Silverback Systems
Cadence PKS. We followed the layout guideline provided by Denali.
Simplex QX is used for RC extraction. Calibre is used for DRC/LVS.
Synopsys TetraMax. No issues.
- Andy Le of Toshiba
Cadence Silicon Ensemble, Mentor Calibre, SynTest
- Bidyut Parruck of Azanda
We have not reached P&R yet.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did the Denali controller require any special I/O pads? Did Denali
> provide you with help in this area?
No special I/Os needed.
- Bill Sullivan of Agere Systems
Yes. SSTL. No help was requested from Denali.
- Joe Coyne of Infinicon Systems
We used our pads. No.
- [ An Anon Engineer ]
We use custom-designed pads from TriCN.
- Vaughn Langston of Corrent Corp.
Databahn did not require any special I/O pads. We used the standard SSTL2
I/O pads for DDR-SDRAM which our ASIC foundry has provided for us.
- Takuro Takahashi of NTT Electronics Corp.
We used the standard Xilinx IO pads. They worked fine. We did need to
optimize the output restance using the on chip features, however.
- Warren Miller of Avnet
It is required to have special DDR pads but there was no additional
requirement from Denali. To implement these Pads we got help from Denali.
- Frank Pitter of Infineon
Yes
- Majid Shushtarian of Quicksilver Technology
Yes. We worked together with the ASIC vendor and Denali to trade-off timing
characteristic of I/O.
- Barry Katz of Signal Integrity Software, Inc.
Yes. SSTL2 DDR cells. Xilinx and Denali both had to provide help.
- [ An Anon Engineer ]
We will be working with Denali to get the special I/O pads as soon as
we start with our synthesis and place and route efforts.
- Abhijeet Ghadje of Netcontinuum
Yes, ours requires special IOs. Denali did help.
- Brad Howe of Altera
Required typical SSTL2 pads. We had to source that ourselves.
- Hugh Chow of ViXS Systems
SSTL pads are required. We are not using Denali SSTL pads.
- WeeHow Lim of Hewlett-Packard
Yes. No assistance from Denali.
- [ An Anon Engineer ]
No, Denali did not get involved with the pads. It only requires generic
pads which most vendors offer (bidir, output, input pads, and clock pads)
One should do a top-down budget of the timing for pad, wire bond, boards
traces, and clock skews etc. Denali rest this on the customer.
- Phil Lowe of Azul Systems
No, as IBM had SSTL-2 in both libraries. In any case its not Denali, it's
the DDR-SDRAM standard. Denali provides what they call I/O cells, which is
the surrounding logic of the I/O pads tight together to ease timing closure.
Again, with IBM methodology this is taken care of almost automatically.
- Dror Har-Chen of Silverback Systems
We use SSTL-2 IO cells which were supplied with the library. Denali
provided design guidelines for the IO cells and provide cunsultation
to obtain timing performance and spec requirements.
- Andy Le of Toshiba
Nothing out of ordinary - needed SSTL I/O. We did not ask Denali for help.
- Bidyut Parruck of Azanda
No more so than any other DDR-SDRAM controller. They have provided
contact information for SSTL2 pad vendors.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did the controller meet Denali's size estimate? (i.e. number of gates)
Yes.
- Bill Sullivan of Agere Systems
Yes.
- [ An Anon Engineer ]
It almost met the size.
- Takuro Takahashi of NTT Electronics Corp.
FPGA Design -- We hit our target of around 2000 slices (2150).
- Warren Miller of Avnet
Yes.
- Frank Pitter of Infineon
Yes, we were on budget for area. I don't recall the size, however.
- Brad Howe of Altera
We didn't get an estimate.
- Hugh Chow of ViXS Systems
It was not an issue.
- [ An Anon Engineer ]
Yes.
- WeeHow Lim of Hewlett-Packard
Yes, the gate count was fairly inline with the orignal estimate, which is
depending on the datapath width, FIFO depth, freq. of operation.
- Phil Lowe of Azul Systems
Yes
- Dror Har-Chen of Silverback Systems
Very close (+/- 5%)
- Andy Le of Toshiba
Yes, it was small enough for it not to matter.
- Bidyut Parruck of Azanda
Yes.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did Denali provide good customer support?
For the most part, yes. But there were a few occasions where customer
support emails would go into a black hole. Usually,
The biggest complaint I had while integrating this design was, with every
new release of their code (we had several releases due to a Denali bug,
Logicvision changes, addition of ext mem BIST, etc.) they would rearrange
the addresses of all the control registers. Every new release it was
probably a 2-3 day hit to change all of the register docs, change the
register programming routines used by DV, regress everything to make sure
it was working. Not as plug and play as I would have liked. Especially
considering that with each release the databahn interface was changing
little if at all.
- Bill Sullivan of Agere Systems
In most cases customer support was very good.
- Joe Coyne of Infinicon Systems
Yes.
- [ An Anon Engineer ]
Denali's customer support has been excellent. I can typically get a
response to questions within a day.
- Vaughn Langston of Corrent Corp.
Yes.
- Takuro Takahashi of NTT Electronics Corp.
FPGA Design -- Denali provided excellent customer support. They worked with
us to select features and to optimize data capture and IO pads. They saved
us alot of time. They are experts at this stuff.
- Warren Miller of Avnet
We got very good support from Denali. This was especially important since
it was our first DDR project.
- Frank Pitter of Infineon
Yes
- Majid Shushtarian of Quicksilver Technology
Yes! We're pleased with their prompt response on any issues that we've had.
- Abhijeet Ghadje of Netcontinuum
We are positive about the pre-sales support (they react in timely matter,
accurate), we have no experiences with after-sales support yet.
- Wiegert Wiertsema of Philips Semiconductors
Yes, outstanding.
- Brad Howe of Altera
We bothered them a lot. They were always willing to help.
- Hugh Chow of ViXS Systems
It is quite satisfactory in terms of support.
- WeeHow Lim of Hewlett-Packard
No.
- [ An Anon Engineer ]
Yes, I'm reasonably happy with the current support, they are good folks to
work with.
- Phil Lowe of Azul Systems
VERY GOOD. EXCELLENT.
Dealing with many vendors you are so tired with fighting over your piece of
support. Not the case here. Being a startup we gave the big speech of "be
good to us, we'll grow and all of us will gain", but I'm actually sure it
didn't make any difference. Whenever an issue comes up (and they do, don't
get me wrong) they track it down, answer to the point, resolve or explain
proper usage. They assisted in placement and also timing closure. They
assisted us by changing stuff for us, being IBM specific items (we are still
too early even with the second chip to take advantage of their own work with
IBM), functional changes we asked for and even cosmetics.
They are open to our criticism, and they improve upon it. As long as they
keep it going like that I can say only that it is customer support as it
should be.
- Dror Har-Chen of Silverback Systems
Yes. Excellent support and we can always have AEs and managers on-site.
- Andy Le of Toshiba
Yes - they were excellent. We received a lot of support for understanding
their controller as well as placement of various blocks.
- Bidyut Parruck of Azanda
EXCELLENT
- Barry Katz of Signal Integrity Software, Inc.
Yes. We are working with quite a variety of IP vendors on this design
and I can honestly say that Denali has been by far the best in terms of
support.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Did you tape-out? Did you get to silicon? production? How many chips?
Not yet.
- Bill Sullivan of Agere Systems
No.
- Joe Coyne of Infinicon Systems
Not yet
- Barry Katz of Signal Integrity Software, Inc.
Yes.
- Helena Zheng of 3DSP
Not yet (next week).
- [ An Anon Engineer ]
We have three chips in the field that use Denali's controller with two
of them being currently in production.
- Vaughn Langston of Corrent Corp.
Yes. We have already received the engineering samples and we could achieve
the target performances as we expected from the actual silicon.
- Takuro Takahashi of NTT Electronics Corp.
FPGA Design -- We sell the design as part of our reference design. Visit
http://www.AvnetAvenue.com to see the details.
- Warren Miller of Avnet
Not yet.
- Frank Pitter of Infineon
No
- Majid Shushtarian of Quicksilver Technology
Not Yet.
- Abhijeet Ghadje of Netcontinuum
No, did not tapeout.
- Brad Howe of Altera
Yes. First pass silicon already shipping 18 months after start of ViXS.
- Hugh Chow of ViXS Systems
Not yet but soon.
- WeeHow Lim of Hewlett-Packard
Yes. Their memory controller was one of our risk items.
- [ An Anon Engineer ]
Not on current project.
- Phil Lowe of Azul Systems
Yes. Yes, we have populated development boards in house and also with
customers. Can't tell you much about numbers. Sorry.
- Dror Har-Chen of Silverback Systems
Not yet, due to product spec change.
- Andy Le of Toshiba
Yes. Yes. About to go to production.
- Bidyut Parruck of Azanda
No. Our current schedule is approximately the end of this year.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Were there any surprises you had wished you'd know about beforehand?
Some issues with the command and data FIFO documentation.
- Helena Zheng of 3DSP
No.
- Bill Sullivan of Agere Systems
Better selection of the delay line elements would have given more margin
and eased STA.
- [ An Anon Engineer ]
Nothing in particular.
- Takuro Takahashi of NTT Electronics Corp.
It would have been nice if the networking market didn't crash in on us. Not
as many designs are going on as we would have liked, but that's not a Denali
issue. :)
- Warren Miller of Avnet
No surprises.
- Frank Pitter of Infineon
Not really.
- Brad Howe of Altera
:) Nothing fatal.
- Hugh Chow of ViXS Systems
Hopefully not.
- WeeHow Lim of Hewlett-Packard
I wish we were working with silicon proven IP. We had several late bugs
come in (found by other Denali customers) that really caused turmoil with
our schedule.
- [ An Anon Engineer ]
We found some features that were removed after engaged in business
relationship. This should have been flagged ahead of time.
- Phil Lowe of Azul Systems
On DDR-SDRAM devices themselves, not from the controller side. The overall
SI might have looked slightly different, but it doesn't change the Denali
controller much, and what we asked for was already changed.
- Dror Har-Chen of Silverback Systems
We need to pay detailed attention to the layout planning to obtain the
needed performance.
- Andy Le of Toshiba
Denali controller has built-in digital DLL. Despite Denali warning us
about special placement requirements for the DLL and related circuitry,
we had a few surprises during final stages of tapeout and initial bring-up.
They did do excellent job in supporting us through this phase.
- Bidyut Parruck of Azanda
No.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Licensing? What type of NDA's contracts, royalties were required from
> the Synopsys & Denali mem controller IP people you dealt with?
I believe we paid a one time fee for use of the block. No per chip
royalties.
- Bill Sullivan of Agere Systems
Normal stuff, fairly easy process. We only dealt with Denali in this, not
Synopsys.
- Qasim Shami of LSI Logic
A general licensing agreement for Databahn was negotiated (no royalties)
and a mutual NDA was completed as part of the work up-front.
- [ An Anon Engineer ]
NDA: It was a regular NDA. Royalty: Not required.
- Takuro Takahashi of NTT Electronics Corp.
Since it is an FPGA design for Xilinx FPGAs, we use the standard FPGA
licence agreement.
- Warren Miller of Avnet
We did sign an NDA to get further details about Denali's DDR Controller
before we decided to buy the core. We were impressed with Denali's
simplified ASIC Interface and hence did not even think twice to go back
and check what Synopsys offered. Yes! We did have Synopsys come over
and brief us with their IP solution.
- Abhijeet Ghadje of Netcontinuum
Single ASIC/ unlimited instantiation license. No royalties.
- Bill Sexton of Texas Instruments
I did a one-time purchase of Denali's controller. I did not deal with
Synopsys at all.
- Brad Howe of Altera
We do not use Synopsys so no comment there. We have an one-shot up front
licensing contract with Denali. In fact, we were among the first group of
customers Denali has for their controller.
- Hugh Chow of ViXS Systems
The license was for per project based, with no royalties, and unlimited
instances.
- Phil Lowe of Azul Systems
No special NDA - very basic stuff (and they are flexible allowing us send
RTL to the formal verification tool vendor to clear issues with it). No
royalties, we have a fixed price.
- Dror Har-Chen of Silverback Systems
For Denali, we pay only license fee and no royalty.
- Andy Le of Toshiba
Nothing out of ordinary. We do use IP from various sources.
- Bidyut Parruck of Azanda
We signed a mutual NDA with Denali. No royalties were required.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> What was the main value of the Denali solution? Why did you choose it
> over the Synopsys DesignWare memory IP solution?
Main value of Denali's solution was to save us having to design an FCRAM
interface ourselves. I actually wasn't on the project when the decision to
use Denali was made so I don't know why it was chosen over Synopsys.
- Bill Sullivan of Agere Systems
Synopsys controller did not meet performance requirements at the time we
made the choice.
- Joe Coyne of Infinicon Systems
Did not know about Synopsys solution.
- Helena Zheng of 3DSP
Denali has supplied us memory models and we were happy with their support.
Initial discussions with Denali for the project were positive, and
references for DataBahn were also positive.
- [ An Anon Engineer ]
Denali has been flexible to meet our requirements, etc. Since Denali
supports the simulation models as well, it is easy for us to fit into our
simulation environment.
- Takuro Takahashi of NTT Electronics Corp.
We selected Denali because they are the experts. Their DataBahn solution
allowed us to select exactly the right features. The controller works
great. Its less filling too (small number of FPGA gates). What a deal.
Maybe they could do one of those commercials...
- Warren Miller of Avnet
We also evaluated the IP from Synopsys, but we decided to go with Denali
although the Synopsys controller would have been for free. We chose
Denali due to the following reasons:
- Synopsys provides only an AHB interface
- Denali supports delay compensation
- Denali supports ECC
- Denali delivers RTL while Synopsys has a complicated way using
CoreConsultant to generate a mapped netlist.
Denali supports not only DDR1, but all other DDR types as well.
- Frank Pitter of Infineon
Easy to interface, proven technology w/ latest in technology ASIC tapeouts,
assured backend support, FPGA emulation support, customizable IP, highly
programmable interface, dedicated team and expertise on Memory Interfaces.
- Abhijeet Ghadje of Netcontinuum
Faster design turn-around-time in ever changing memory market is Denali's
main value. I think that this value is much higher for ASIC than in FPGA
design like mine. I was not aware at the time that Synopsys memory IP was
available or not.
- [ An Anon Engineer ]
TurnKey, configurable solution for very high speed controller w/ hardenable
PHY module at the ASIC supplier of my choice.
- Bill Sexton of Texas Instruments
We selected Denali as a potential controller provider for Philips because
they have the intrinsic power to provide future proof controllers. Thanks
to their memory modelling activity, they have built relationships with
memory vendors and memory users. They also have an own marketing research
activity.
- Wiegert Wiertsema of Philips Semiconductors
Denali had the design in production, and I had prior experience with them
that was good.
- Brad Howe of Altera
Time to market. we actually have more memory expert in house than Denali
due to our graphics root. Back when we picked Denali, we weren't aware of
controller solution from DW.
- Hugh Chow of ViXS Systems
Good support give customer the confident element.
- WeeHow Lim of Hewlett-Packard
We believe that the Denali controller will be most prevalent and industry
standard.
- [ An Anon Engineer ]
The Synopsys DW DDR IP was too simplistic in its timing model, not suitable
for high speed operation 133+ MHz.
- Phil Lowe of Azul Systems
I would recommend it, and probably use it if I need what they offer.
Probably I'll feel confortable with the company for other stuff.
- Dror Har-Chen of Silverback Systems
I don't remember having Synopsys as an option at the time we started. We
looked for controllers found Denali and a bunch of unknowns. Since we're
not using Synopsys we haven't go to know their option, and I'm not sure it
is accessible without owning the Synopsys tools.
- Dror Har-Chen of Silverback Systems
Proven and widely used. Their technology and solutions are updated
quickly.
- Andy Le of Toshiba
Lack of built-in digital DLL. Concerns about Synopsys ability to support,
based on past experience.
- Bidyut Parruck of Azanda
I have not investigated the Synopsys solution. The main value of the
Denali solution is that they provide the entire package including memory
models, RTL source code access, BuildGates scripts, customized
documentation, embedded DLL, customized internal interface, and
excellent support. They also allow us to reconfigure the core via their
web site and receive as many code drops as necessary prior to tapeout.
- Mike Peters of Digeo
---- ---- ---- ---- ---- ---- ----
> Would you use Denali's solution again? Would you recommend Denali to
> others?
Yes, I would use them again. Yes, I'd recommend to others.
- Bill Sullivan of Agere Systems
Depends on silicon success.
- Joe Coyne of Infinicon Systems
The project has not been completed yet, but judging by the engagement and
experience so far, I would probably say yes.
- Qasim Shami of LSI Logic
We will wait till we have silicon -- if all goes well, yes. Yes.
- [ An Anon Engineer ]
We are currently working on the fourth chip in which we have used
Denali's DDR SDRAM controller IP. The first three used 64-bit controllers,
and this current one is using a 32-bit controller. I believe we were
the first customer to actually get silicon back using this IP, so on the
first chip the IP was very new, and we had lots of problems with it.
However, Denali has improved the design drastically, so that now it's quite
stable and much friendlier to layout. Denali's support has been excellent,
and, overall, I think our experience with using Denali's controller IP has
been very positive.
- Vaughn Langston of Corrent Corp.
Yes.
- Helena Zheng of 3DSP
We want to use Databahn again for our next design opportunity. We recommend
Denali to other companies.
- Takuro Takahashi of NTT Electronics Corp.
We recommend Denali every day to our FPGA customers. We have not had any
complaints so far.
- Warren Miller of Avnet
We will again use Denali for further project and I would recommend this also
to others since they are very experienced with DDR, deliver good quality,
and give a good and committed support.
- Frank Pitter of Infineon
Many of the above questions better be answered after tapeout.
- Majid Shushtarian of Quicksilver Technology
Yes!
- Abhijeet Ghadje of Netcontinuum
Yes
- Bill Sexton of Texas Instruments
Yes, and yes.
- Brad Howe of Altera
Probably not. As stated, we have very deep memory expertise. We used
Denali mainly for time to market when ViXS started. (ViXS had always been
open to Denali with our intent. Though when told Sanjay this, and he
wanted to kill me. ;) Though we would highly recommend Denali to others.
- Hugh Chow of ViXS Systems
Yes. Most definitely for FPGA design at least.
- [ An Anon Engineer ]
Yes.
- Barry Katz of Signal Integrity Software, Inc.
Yes provided the management agreed to spend $ on the IP. I would definitely
recommend Denali's IP.
- WeeHow Lim of Hewlett-Packard
Yes. The jury is out about the improvements in the area of support and
documentation. I really look forward to the improvements Denali claims
they have made in the area of delivery, support, and documentation of
their product.
- [ An Anon Engineer ]
Yes. Sure.
- Andy Le of Toshiba
Absolutely yes! Overall the Denali DDR controller is working for us and
we are planning to use them for our next generation product.
- Bidyut Parruck of Azanda
Of course, I'll have to reserve some judgement until after we have working
chips. However, at this point, I have been completely satisfied with our
decision to use Denali and I'd have no reservations about recommending them
to others.
- Mike Peters of Digeo
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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