( ESNUG 414 Item 11 ) ------------------------------------------- [06/18/03]
Subject: Cadence Retribution & Users On The Diva, Dracula, Assura DRC Tools
> So I was surprised when I saw Cadence and Mentor tied for first place, at
> 38 percent each, in the 2001 Dataquest DRC market share numbers. How
> could this be when so many users had such a low opinion of the Cadence
> DRC tools?
>
> "Those Cadence DRC numbers are B.S. because Cadence hasn't had any new
> DRC sales in that time. It's all those old 3 year FAM license deals that
> Cadence did in '98," replied Gary Smith, Chief EDA Analyst at Dataquest.
> "This is just license renewals with their prices raised. In some cases
> it was a 3x raise."
>
> So pretty much, Cadence is running on fumes in DRC now.
>
> - from http://www.deepchip.com/gadfly/gad052803.html
Editor's Note: I had a funny experience because of this column. It was
published 5 days before DAC started this year. I was invited by Cadence
to attend their annual press & analysts DAC dinner at the Nixon Library
until, 3 hours before the dinner was to start, I got a phone call
from Cadence PR disinviting me! I was told "don't bother showing up,
because if you do, we will turn you away." Ostensively, the Cadence PR
lady said the dinner was "full", but I later howled with laughter when I
found out that the first question at the dinner table Ray Bingham, the CEO
of Cadence, asked both my publisher and my editor-in-chief at EE Times
was "Why do you publish a column by John Cooley in EE Times?" :) - John
From: John Weiland <jweiland=user company=intrinsix spot calm>
Hi, John,
Supposedly Cadence does not even support user benchmarks against Calibre or
Hercules any more because they know they will lose. I understand the
Cadence answer is that the time users should concern themselves with is
not the time needed to find the errors, but the time needed to produce a
correct design, of which running the DRC is only a part. I think Cadence
claims that despite their slower times to get the list of errors, their
capability at debug (where you painstakingly look at each error and either
fix it or mark it as bogus) is so much better that you will still get a
correct chip faster. It sounds like there is not universal agreement on
this point.
- John Weiland
Intrinsix Corp.
---- ---- ---- ---- ---- ---- ----
From: [ Just Shoot Me ]
Hi, John,
You should keep this anonymous if you use any of it.
W.r.t. Assura: You are right on target here!
The only thing protecting Assura in our group is the convenience of
integration into the Virtuoso environment and the man-years invested in
custom extraction decks for RF and analog use.
For chip level DRC -- it's dead -- the foundries don't supply golden
decks for Diva or Assura anymore.
For chip level LVS -- well -- it failed to complete at all on our last
chip. Thank heavens for Calibre.
I've given up on Assura. I'm not even bothering to waste my time
working with Cadence to fix it anymore.
And, while I'm having a rant....
By inference, there is something very bad happening inside Cadence's
quality assurance programs. Assura is the worst, but the frequency of
'core dumps' from most of the Cadence tools that we run is increasing.
Now, call me naive, but this is the 21st century, there are good software
engineering methodologies out there and excellent tools for tracking down
memory leaks and pointer problems. I'm OK with tools having bugs or not
quite giving the quality of result desired and working with the vendor
to improve the issue, but core dumps just indicate really poor software
engineering foundations, a lack of decent regression tests and a poor
quality culture.
Perhaps Cadence needs an Intel-like user driven program, "No Core Dumps
Inside"!
- [ Just Shoot Me ]
---- ---- ---- ---- ---- ---- ----
From: Federico Aglietti <f.aglietti=user company=ipitec.it>
John,
We are using Cadence DRC tools on a SoC without any problem. We are going
to use in future.
- Federico Aglietti
Ipitec (Atmel) Rome, Italy
---- ---- ---- ---- ---- ---- ----
From: John Reeder <jreeder=user company=microsemi spot calm>
Hi John,
Diva and Dracula are far from dead, and are still supported by many
foundries. If you had asked me a couple of years ago, I too would have
thought them dead.
But the reality is that Dracula and Diva are the work horses that keep
going and going. This is because, many designs do not need the performance
of 0.2 and smaller gate lengths. These include the logic glue chips and
the analog chips that support the large chips that get media attention. And
since these newer processes are much more expensive than the older processes,
it is more economical to choose an older process. These economical older
processes have not been rewritten in DRC Calibre or DRC Hercules rule decks.
They are still written and supported in Dracula and Diva DRC rule decks.
I expect that Dracula and Diva will be in use for a long time to come. In
this economy, design companies are working to save money where ever they
can. In addition to saving money on using an economical foundry process,
they can also save money by using Dracula and Diva. They are saving money
by not having to pay recurring engineering costs rewriting the DRC rule
decks in Calibre and Hercules. And Dracula and Diva cost less than Calibre
and Hercules.
- John Reeder
Microsemi Corporate Center Irvine, CA
---- ---- ---- ---- ---- ---- ----
From: Nicco Bhabu <nicco=user company=chipx spot calm>
Hi, John,
Dracula is frustratingly slow, with a non-existent support. Their brief
error messages NEED technical support for debugging. Calibre is several
orders of magnitudes better in terms of execution speed and error details.
- Nicco Bhabu
Chip Express
---- ---- ---- ---- ---- ---- ----
From: An Unkown Person <a123b456c=user company=aol spot calm>
KILL' EM!!!!!! WILL YOU, PLEASE!!!! KILL THE .......!!!!
- An Unknown Person
---- ---- ---- ---- ---- ---- ----
From: Mark Rencher <markr=user company=pivotalenterprises spot calm>
John,
The Cadence poor showing in the physical verification market is a classic
example of you get what you paid for.
The Cadence business strategy of providing large price breaks to large
customers in the form of FAM agreements essentially provided a very low
cost product, which in turn produced a sub-par technical product. Coupled
this business decision with an enormous amount of sales/marketing to make
up the difference (remember the name changes Diva, Vampire, Assura, but the
same old technology).
To give Cadence credit, they did have a go at trying to improve the product
by focusing on the AMS market. The fundamental issue is that AMS designs
are very hierarchical and Vampire just rolls over in it's grave when it
comes to hierarchical designs. Just have Assura stream out a hierarchical
design and see what you get.
So, Cadence and their customers got what they paid for.
Let's just hope that Mentor Graphics and Synopsys don't make the same
mistakes.
There is a multi-billion dollar market relying on physical verification to
"get it right the first time".
- Mark Rencher
Pivotal Enterprises Gilbert, AZ
( ESNUG 414 Networking Section ) -------------------------------- [06/18/03]
Austin, TX -- Mentor Graphics seeks a highly experienced Calibre user to be
a Calibre FAE in the Austin area. <mike_walsh=user company=mentor spot mom>
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