( ESNUG 414 Item 1 ) -------------------------------------------- [06/18/03]
From: Robert Clark <rac=user company=paramanet spot calm>
Subject: User Sees Tenison Verilog-to-C VTOC Benchmarks 14x Over VCS 7.0
Hi John,
I recently benchmarked VCS 7.0 vs. Tenison's cycle accurate compiled Verilog
RTL simulator called VTOC. (See http://www.tenison.com)
When we started our SoC design, we thought we would create a cycle accurate
reference model, before coding Verilog RTL. We quickly realized that with
our headcount constraints and short product schedule, we wouldn't be able to
maintain two versions of our design, i.e. one in C and one in RTL.
We felt emulation was out of the question, because of the $cost and amount
of support required to maintain the emulation system, bring up the initial
RTL model, and maintain the RTL model as changes are made.
Therefore, we looked for a C++ modeling tool that could offer a good
compromise between these approaches -- automatically produce the C reference
model from the source Verilog RTL without the hassle and cost of hardware
emulation, albeit also with a tradeoff in performance.
What I found with VTOC, is that no changes were needed to our Verilog RTL
other than using behavioral RAMs in place of the vendor Verilog RAM models,
to start running the simulations. (We don't put blocking assignments or
timing information in our Verilog RTL.) Since our test benches were written
in C++, it was easy for us to "link" to the C++ code generated by VTOC.
My benchmarks were on moderate size RTL blocks, but I don't see why this
would not work for the 3 ASIC/FPGA designs we currently have in house. Our
software team created a "register only" model of our SoC, so that they
could start the software design in parallel. If we had VTOC earlier,
we could have replaced the "register only" model with the cycle accurate
model created from the Verilog RTL.
From our experience, VTOC will never replace timing accurate simulations,
but it certainly would help software and functional RTL verification.
I chose 2 Verilog RTL blocks from one of our FPGA designs to eval VTOC.
The test bench for benchmark1 was written entirely in C++. After writing
a C++ interface from the test bench to the DUT, I was soon running VTOC
simulation benchmarks. The test bench for benchmark2 was a mixture of
C++ and Verilog.
RTL lines VCS 7.0 VTOC Speedup X
--------- -------- ------ ---------
benchmark1 1750 38.5 sec 1.3 sec 29.62
benchmark2 5100 1833.0 sec 128.0 sec 14.32
VTOC was able to compile both benchmarks without any modification to our
Verilog RTL source. Benchmark1 has a single clock with 1024 bits of RAM.
Benchmark2 has two clocks and 308 Kbits of RAM.
All simulation benchmarks were run on a RedHat Linux 7.2 machine with no
other processes running. The machine has 512 MB of DDR 266 RAM with an AMD
Athlon XP 1900+ CPU. Speedup is referenced to the VCS 7.0 FCS simulator.
- Robert Clark
Parama Networks Santa Clara, CA
Editor's Note: Just a technical reminder that VTOC is a *cycle-based*
simulator. That is, it throws away all *timing* information and runs
only *functional* simulations. (Sometimes people forget this.) - John
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