( ESNUG 413 Item 5 ) -------------------------------------------- [05/29/03]
Subject: Beaucoup Chip Designers Chime In On The FPGA vs. ASIC EDA Debate
> For 2001, Dataquest reported that the ASIC market was $16.6 billion while
> the FPGA market was $2.6 billion.
>
> What's more interesting is that the 2001 ASIC EDA market was $2.2 billion
> while the FPGA EDA market was $91.1 million. Nope, that's not a mistake.
> It's ASIC EDA and billion versus FPGA EDA and million. Do the math and
> you'll see for every dollar spent on an ASIC project, roughly 12 cents
> of it goes to an EDA vendor. For every dollar spent on a FPGA project,
> roughly 3.4 cents goes to an EDA vendor. Not good.
>
> It's the old free milk and a cow story according to Gary Smith, the Senior
> EDA Analyst at Dataquest. "Altera and Xilinx have fouled their own nest.
> Their free tools spoil the FPGA EDA market," says Gary. "EDA vendors know
> that there's no money to be made in FPGA tools."
>
> So FPGAs are the slums of the EDA world. If design does go all FPGA as
> David & Andy warn, the $2.3 billion EDA industry will shrink down to $628
> million. That's what 3.4 percent versus 12 percent can do to you. Ouch.
>
> - from http://www.deepchip.com/gadfly/gad042803.html
From: Gerrit Van Loo <gerrit.van.loo=user domain=globespanvirata spot calm>
John,
You have just got yourself some HOT potato!!! I would not like to be at the
other end of an FPGA versus ASIC discussion. The idea that FPGA's are going
to replace ASICs is rubbish. The only thing that FPGA's are replacing is
smaller low-volume ASICs. It is the definition of 'smaller' which is
shifting each year. So FPGA's are more & more replacing'smaller' ASICS
where smaller is getting bigger each year.
As most engineers like figures, here are some:
- We are building an emulation system using FPGA's for our ASIC.
- We need about 3-4 FPGA's each $5000, to emulate our ASIC.
- Our customers are already complaining if our ASIC cost is above $25.
Need I say more??
- Gerrit van Loo
GlobespanVirata Cambridge, England
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From: Steve Padnos <spadnos=user domain=atheros spot calm>
John,
The Dataquest numbers are not passing some simple sanity checks. I just went
to Yahoo and it looks like Synplicity revenue for the last 12 months was
over $40 million. That is virtually all FPGA. I don't know what percentage
of the FPGA synthesis market they have. But when you add competitors,
simulators, P&R, etc. the Dataquest numbers seem suspicious.
- Steve Padnos
Atheros Communications, Inc.
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From: Ken Ryan <ken.ryan=user domain=smiths-aerospace spot calm>
John,
At our site we let all of our ASIC tool licenses lapse and will probably
never do anything but FPGAs again. Masked gate arrays have already lost to
modern FPGAs, and even a simple standard-cell chip that will give you speed
and power advantages has ASIC EDA costs far too high when you have a typical
production run of a few hundred devices. I believe FPGAs will never make
ASICs obsolete, but I think ASIC designs will be confined to a smaller and
smaller number of elite who can afford the higher costs of ASIC EDA.
I dearly miss the power and flexibility ASIC design tools such as Synopsys
(and the "freedom" of a bare square of silicon), but it's certainly true
that as long as FPGA tools are "good enough" for most designers and FPGA
manufacturers subsidize tool development with chip sales there is little
incentive for a third-party company to attempt to bridge that gap. I wish
the best of luck to companies that try!
- Ken Ryan
Smiths Aerospace
---- ---- ---- ---- ---- ---- ----
From: [ The Great Pumpkin ]
Hi John,
If you use this, please keep me anonymous.
Since the volumes in our industry run in the millions and the cost pressure
is very high, we will not be using FPGAs in products in the foreseeable
future. We are however using them for prototyping and testing new ideas and
providing early platforms for firmware development.
I am one of two engineers doing this work in a department of about 25 ASIC
designers. For the ASICS we use a pretty standard tool set - NC, Primetime,
Design Compiler, etc - all running on a room full of servers with LSF for
queue management and a home grown version control system. We use as much of
this infrastructure for the FPGA work as we can.
I have used both vendors tools but most recently have been using Altera
Quartus for Place & Route and Mentors Leonardo Spectrum for synthesis. Our
current design uses about 60,000 Logic Elements in the biggest Stratix part
available. Most of the RTL, which is all in Verilog, is transferred
directly from that planned for the ASIC with a minimum of changes. It
implements about 25% of what goes into the ASIC.
I have had some issues with the Leonardo, but no more so than we have
experienced with the Cadence or Synopsys tools. We have found workarounds
and scripted the synthesis process.
I can not say the same for the Altera tool. There is a hidden cost in the
"free" or low cost software from them. The short description is that it is
not a professional level tool.
The long list includes the following.
- Altera Quartus is a windows program that is poorly ported to UNIX and
poorly supported. As a windows program in fails occasionally for no
discernable reason.
- Our servers are HP but the FEAs do not have access to HP workstations
and from the number of bugs that I have found, neither does Altera
test Quartus on HPs before release. I am not sure that their internet
support have access to HP workstations either.
- Quartus actually creates a windows directory on your home directory
which contains a "registry". That does not work very well on Windows
and it is even worst on a UNIX system.
- We purchased some IP from Altera but they were never able to get the
license stuff straightened out on the HPUX so we must do our top level
Place & Route on a Linux box. Because of the registry stuff, I have
not been able to get the P&R working with the LSF queue on a Linux box.
- Altera claims to support tcl scripts but their version of tcl is like
none other I have seen and it is very awkward to use.
- Altera claims to support PrimeTime and they do output a netlist and SDF
but the timing triplets contain three identical numbers. The FEA says
that these are pessimistic maximum. So there is no way to check for
minimum violations.
- Altera claims to support NC-Sim and do produce an annotated netlist but
again all times are pessimistic maximum. Consequently you can have a
design pass simulation and fail in the lab and visa versa.
- Altera claimed DDR support when the part was announced. The first
application note on DDR was about six months later and was wrong. I got
a copy of a lab report about two months later and it was almost right.
The final Altera application note was correct about four months later.
Quartus did not correctly support DRR until about 6 months after parts.
I could go on but I've said enough. Sorry for venting, but my experience
with "low cost" FPGA software proves again "There ain't no free lunch".
- [ The Great Pumpkin ]
---- ---- ---- ---- ---- ---- ----
From: Joe Gianelli <jgianelli=user domain=synplicity spot calm>
Hi John,
Yes, EDA is in for a big change over the next few years as FPGAs expand
in use.
- Joe Gianelli
Synplicity EDA
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From: Jim Kornell <jkornell=user domain=coldspringeng spot calm>
John,
Thanks for your ESNUGs. Great education for guys like me, relatively new
to the field and just getting a feel for how the industry works. I've got
to say, this FPGA EDA vs. ASIC EDA issue reminds me of the software world
back in the 80's. Want to buy a C compiler from DEC for $10K?
- Jim Kornell
Cold Spring Engineering
---- ---- ---- ---- ---- ---- ----
From: Erik Jessen <ejessen=user domain=xiran spot calm>
John,
Some points:
1) LSI, IBM, etc. give away free tools when you use their silicon, just
like Altera and Xilinx. What you say about some, you say about all.
The root cause of vendors writing their own tools & giving them away is
that EDA vendors didn't address their needs. Writing tools is an ASIC
house's last, not first, choice. I blame the EDA industry itself for
not getting their big customers to out-source EDA tools.
2) Have you ever actually taken a look at those FPGA tool suites you say
are robbing the EDA industry of income?
Altera's tool pack includes Synplify and Modelsim, and I expect they
got paid for it. Other FPGA/CPLD tool packs are similar.
3) In looking at your numbers, what you're really saying is that FPGAs are
a much more cost-effective solution for customers, and that usually
means that market will grow. FPGA tools don't require a small army of
employees and consultants to care and feed them, which is where the
expense really lies.
4) I believe Synplicity's existence proves that EDA vendors can make money
in the FPGA market. I'd argue the same for Mentor's Modelsim, but I
don't know how many seats of Modelsim are used for FPGA vs. ASIC
development.
I suspect the ASIC EDA vendors are not managed as efficiently as FPGA
EDA vendors.
This reminds me of a story I read in a management-training class. Ford had
managed to get their shipping & recieving from 600 people down to 400, and
they were pretty proud. Then Ford bought Mazda (IIRC), and they visited
Mazda, who did the work of the 400 with 2 people, because they'd radically
reorganized how they worked.
Perhaps the FPGA tool vendors have a radically better way of developing EDA
tools, and so they can sell their tools for less, and still make a profit.
I know that, years ago, Modeltech had a small and very proficient design
team. Maybe they still have that corporate culture, and so can succeed
where Synopsys and Cadence can't?
- Erik Jessen
Xiran
---- ---- ---- ---- ---- ---- ----
From: Robert Sadler <rsadler=user domain=amis spot calm>
Hi, John,
I really doubt that the ASIC industry at this point is in a lot of trouble
with FPGAs. It pretty much boils down to economics. As products that
have FPGA technology used on the boards ramp up due to demand, there
comes a point where the ASIC cost vs FPGA cost become more competitive.
To stick with a FPGA long term for a product that may have a 5 to 10 year
product life cycle of high volume could mean a significant loss in revenue.
As long as the ASIC industry can continue to produce hi-volume low cost
ASICs for its customers, the economic element of the decision process of
FPGA or ASIC will always cause many FPGA designs to eventually migrate
to an ASIC.
- Robert Sadler
AMI Semiconductor Pocatello, ID
---- ---- ---- ---- ---- ---- ----
From: Doug Walby <dwalby=user domain=ti spot calm>
Hi, John,
I'm an ASIC guy that hasn't done an FPGA in a long time so maybe I'm out of
the loop, but I thought Altera and Xilinx were in the business of selling
chips, not EDA tools. If their free tools make it easier to sell more of
their chips then that would seem like a good business decision, not a bad
one as Gary Smith infers. So what if they spoiled the FPGA EDA market? If
their free tools are adequate to develop products using their chips, why
would they care?? Of course there's no money to be made in FPGA EDA tools,
the whole point of developing FPGAs is paying more in unit silicon cost to
save a lot in tool costs and time to market. If FPGA development were
complicated enough to warrant expensive EDA tools there would be no reason
to develop FPGAs.
- Doug Walby
Texas Instruments
---- ---- ---- ---- ---- ---- ----
From: David Thornhill <david.thornhill=user domain=trw spot calm>
John,
The ASIC vs. FPGA contest will be decided by an economic corollary to
Moore's Law. When ASICs were 25X more dense, 10X faster, and 50X more
expensive than FPGAs, and people needed the speed and density, then they
would pay the big bucks for ASICs. But, over time FPGAs have severely
eroded the density and speed advantage of ASICs, as a direct result of
process improvements and the head-long rush into deep submicron territory
in accord with Moore's Law. Yes, ASICs will always have a speed and
density advantage over FPGAs, but for more and more applications, it just
doesn't matter anymore. But, the cost disadvantage of ASICs vs. FPGAs does
matter, and as both devices become much more expensive to acquire, it soon
begins to matter quite a bit.
Five years ago, perhaps 10% of all applications could be satisfied with
FPGAs; today it's likely 50% that can be, and in a couple of years the
percentage may well be in the 90's. When speed and density don't dominate
the decision process, the FPGA will almost always win the day. Only the
relatively few high volume applications will remain the province of the
ASIC; all others will go to FPGAs. We are rapidly approaching the day
when transistors and clock cycles are free and the numbers available for
ASICs and FPGAs exceed most application requirements. When "that day"
comes and the economics are based principally on non-recurring engineering
costs, the ASIC vendors might as well as go home. Oops, excuse me a
moment, the phone is ringing....it was Actel and Xilinx. Both say "that
day" is today.
- Dave Thornhill
Northrop Grumman Space Technology Redondo Beach, CA
---- ---- ---- ---- ---- ---- ----
From: Jesse Jenkins <jesse.jenkins=user domain=xilinx spot calm>
John,
There doesn't seem to be any mention of the half to one million dollar NRE
for an ASIC in this discussion. Programmable logic has been a great value
from its inception. I think that the EDA picture is just one aspect of
the larger scene.
- Jesse Jenkins
Xilinx
---- ---- ---- ---- ---- ---- ----
From: Paul Fletcher <paul.fletcher=user domain=motorola spot calm>
John,
I can't believe that anyone would think that an FPGA solution could be
cost effective in large volumes. FPGA's are a great proto type platform,
unless you need analog blocks.
- Paul Fletcher
Motorola Semiconductor Chandler, AZ
---- ---- ---- ---- ---- ---- ----
From: Scott Bittle <scott_bittle=user domain=digidesign spot calm>
Hi John,
If these two FPGA designers are correct, why is Synplicity expanding into
the ASIC market? I'm really tired of FPGA designers talking as if "ASICs"
are going away. FPGAs work very well in many situations, and the
capabilities FPGAs have increased over the years, but they are not suited
for large high-performance/low-cost designs. Why even argue? I myself
have done more FPGAs than ASICs, and I try to select the appropriate
implementation on a design-by-design basis.
- Scott Bittle
Digidesign/Avid Technology, Inc. Daly City, CA
---- ---- ---- ---- ---- ---- ----
From: Doug MacDonald <dmacdona=user domain=enterasys spot calm>
Hi John,
I worked at Lockheed Martin for 11 years and all of the contracts that I
worked on were DOD/CIA/NAS/NASA projects.
After reading that Andy Jones of Lockheed Martin was in agreement
with Dave Bishop of Kodak ---I felt Andy is biased being from a company
that has 90% or more Government contracts with basically limited/no
production runs compared to the commercial industry type production runs
of 1000+ per/month for a at least a few years.
So using FPGA's in this government realm is common practice, and also it's
a captive market once the Big Contract is awarded, the government will
purchase all the deliverables.
We at Enterasys have recently finished developing 4 of the largest
custom ASICS in the company's history. The ASIC's sizes range from 600 K
to 2.2 Million gates that are implemented into the newly released N3
Matrix Products. We used Xilinx Virtex I & II FPGAs for the initial
development/debug and to get firmware a workable system sooner. So this
analysis is based on our findings during this project. We are also
giving the FPGA's an aggressive position -- at no time during the
project could we crunch the entire ASIC design into an FPGA that was
available from the vendor at that time. That of course did change over
time. Mostly the limitations using the FPGA's were in reference to the
amount of embedded RAM needed.
To do a comparison we had to overlook issues on both sides:
ASIC issue: Any (Non-metal changes) ECOs after final design are pricey
FPGA issue: reduced speed and having to use 2+ for each ASIC
Also we have to accommodate (more interconnect, footprints,
heat, pwr) for FPGAs.
Assuming the number of designs: 1 design = 1 (ASIC) = 2 (FPGA's)
Using this equation:
Fixed Cost(tools + development) = FC
Variable Cost (Part Cost) = VC
Quantity = Q
ASIC cost per part = ~$50
ASIC Foundry Development Cost = ~$1,000,000
ASIC Tools Cost (for 2 years)
(DC,PT,Formality, NC-Verilog...) = ~$1,000,000
FPGA Cost per part = ~$1000
FPGA Foundry Development Cost = $0
FPGA Tools Cost = $0
So for ASICs: VC*Q + FC = $50*Q + $1,000,000
And for FPGAs: VC*2Q + FC = $1000*2Q + $1000
Solving for Q:
$50Q + $2,000,000 = $2000Q + $0
$2,000,000 = $1950Q
Q = ~1025
Quantity of 1025 designs is the break even number. More than 1025 Designs
then implement into and ASIC -- less than 1025 Designs target FPGAs.
Also to throw a wrench into the whole thing is the human factor -- less
people need for simulation in FPGA efforts more people needed to verify
an ASIC effort by trying to eliminate any changes after finalized
design. And I am sure there are many more on both sides.
The one thing that a few of us did agree on:
Over time if the cost of producing an ASIC keeps increasing faster than
the FPGA cost and the FPGA's (size & Speed) is either not and issue or
can compete with the ASIC--- then the FPGA designs will over-take the
ASIC designs. This is what my father called the "What if" syndrome.
So until "What if" happens its all a numbers game: Quantity and Price.
- Doug MacDonald
Enterasys Networks
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From: Erik Curtis <erik.curtis=user domain=mentor spot calm>
Hi, John,
This article has a fatal flaw. The tools provided by the FPGA vendors are
simple and only work well with small designs. For the FPGA market to
supplant more ASICs, the design complexity of FPGA's will increase greatly.
The FPGA vendors have no interest in making more complex versions of their
software to support these more complex designs. Their only motivation for
making software in the first place is to make more hardware sales. The
complex FPGA designs will require the purchase of complex design tools from
an EDA vendor; this will increase the percentage of FPGA costs going to EDA.
- Erik Curtis
Mentor Graphics
---- ---- ---- ---- ---- ---- ----
From: John Watson <johnw=user domain=qstech spot calm>
John,
Actually, it maybe even worse.
Perhaps from a corporate value viewpoint the way to count in EDA is the
# of design teams * the number of designs accomplished.
We all know the $16.6B ASIC market is composed of far fewer design starts
than the $2.6B FPGA market. So, maybe the $ per design start/completed is
really skewed? What if:
ASICs = 12% * X design starts
FPGAs = 3.4% * 100X or 1000X design starts
Could it be the FPGA guys haven't piddled in their own bed, but are just
so more efficient at getting the work done ASICs are truely hosed.
- John Watson
QuickSilver Technology, Inc.
---- ---- ---- ---- ---- ---- ----
From: [ The Iraqi Information Minister ]
Hi, John,
I must be anon. My predictions on this topic:
1) Behavioral synthesis will be back!
2) FPGA's, FPGA -> ASIC conversions, and MPGA's will surge;
3) The ASIC design job market will remain stagnant;
3) VHDL provides a better foundation for evolution than Verilog;
4) Verilog is to VHDL as VHS was to Beta; (an unfortunate winner)
5) System Verilog is to System C as tape is to DVD;
6) System-C has the greatest potential for revolution
over evolution in the SoC world;
7) Design houses and EDA vendors need to pull their head
out of the sand, and pull their hands out of my pockets!
Revolution over Evolution! Why? Because I'm tired of doing it the old,
hard way.
- [ The Iraqi Information Minister ]
---- ---- ---- ---- ---- ---- ----
From: Frank Wolff <wolff=user domain=eecs.cwru.edu>
Hi John,
Time-to-Market design is also driven by software complexity and physics.
For years, FPGA vendors have well-argued that they have solved the design
& testability complexity issue by having a symmetrical & configurable
architecture and ASICs will soon hit this brick wall.
But as the process technology shrinks, the laws of physics are impacting
FPGA's own brick wall in terms of routing delay and that feared word,
"soft errors." Since the FPGA's logic behavior and routing are configured
by SRAMs, a single soft error can permanently re-route a wire or flip the
logic behavior of a gate from a NAND to a NOR gate which in the case of
ASICs only create a glitch.
Sort of saying, soft logic vs hard logic circuits. FPGA soft error effects
can only be restored by re-configuration of the SRAM. No easy answers but
one can say that both FPGAs and ASICs have entered the Haiku tunnel. :-)
- Frank Wolff
Case Western Reserve University
---- ---- ---- ---- ---- ---- ----
From: Mark Indovina <marki=user domain=improvsys spot calm>
Hi John,
I trust this message finds you well my friend.
I read your thesis on the "FPGA EDA Slums", and I thought I would
share the attached. Feel free to share this data with others.
The document has two pages. Page two show's a simple chart of public
industry data for the ASIC and PLD/FPGA market. As every one knows,
the ASIC market is in a slump (a rather drastic slump from the trend line).
That said, I cannot find evidence of a rush to the FPGA market based on
the industry revenues and more interestingly, from the trend line.
OK, let's ignore the trend data and look at page 1. This page trys
to draw a comparison between a 250K ASIC and an equivalent size FPGA
that has enough gate and internal RAM capacity. You'll find two charts on
this page. The top graph charts only device cost verses unit's (for the
ASIC, I added in the NRE). The bottom graph charts the the device
cost + EDA tools vs unit's.
The take away is that for low volumes, FPGA's overall cost structure does
make sense. That said, a couple of hundred units is not a large volume.
Obviously this is a specific data point, but from my view, I don't think
Synopsys, Cadence, or any of the interesting start-ups will be abandoning
IC/ASIC EDA any time soon.
- Mark Indovina
Improv Systems, Inc. Rochester, NY
[ Editor's Note: Mark's worksheet is #47 of DeepChip Downloads - John ]
---- ---- ---- ---- ---- ---- ----
From: Doug Bailey <dbailey=user domain=chipx spot calm>
Hi John,
This issue of FPGA vs. ASIC hits home for us each time an FPGA company puts
out yet another press release claiming ASICs are dead. Enclosed is our
business analysis when Altera announced their Cyclone product line. You'll
see that for parts in the 250 k usable gates range, the crossover to ASICs
line was in the 819 to 1622 units zone. The tables of data in the analysis
say it all.
- Doug Bailey
Chip Express
[ Editor's Note: Doug's worksheet is #48 of DeepChip Downloads - John ]
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