( ESNUG 411 Item 2 ) -------------------------------------------- [04/23/03]
Subject: ( ESNUG 409 #1 ) Matt Weber's Paper About On-Chip Variation (OCV)
> Paul Zimmer asks: "If your path goes through 20 or so elements, and the
> variation is sort-of random, isn't all-min vs all-max a little extreme?"
>
> Yes it is. The mathematics of it would be that if you had N stages which
> all had equal delay, and you model OCV as independent random variables,
> then the variance goes up linearly with N and the standard deviation goes
> up as the square root of N. So you'd expect 16 equal stages to be about
> four times as bad as one stage.
>
> However any deviation from the above assumptions could make it worse. For
> example, some of the variation can be systematic rather than independent.
> Or not all the stages could be equal in delay. And some of these sources
> of variation are linear, not square-root. So a simplified but moderately
> realistic model of OCV might look something like:
>
> On-Chip Variance (OCV) = a*D + (b*D)/sqrt(N)
>
> where D is the total path delay from the point at which the two paths
> diverged. It seems that most tool (and silicon) vendors simplify this
> further to just a linear model. This isn't quite right, but it's not
> too unreasonable.
>
> - Howard A. Landman
> Riverrock Consulting Fort Collins, CO
From: Philippe Duquennois <philippe.duquennois=user domain=philips got mom>
Hello John,
I am writing about this OCV because I beleive that EDA vendors should
investigate and developp what I would call statistical timing analysis.
Perhaps they are already? Various papers have been written on OCV on
transistor devices. One is even correlating the Idsat with the loation
of the device on the reticle. This paper mentions a 15% variation of
Idsat on the same die. (IEEE Transaction on CAD of IC & Systems,
Vol 21 No5 , May 2002, page 544). This paper explains with many more
details what I am writing below...
For a path with N stages at 0.15xD each, the total absolute error on
the delay is indeed sqrt(N)x0.15xD, but the relative error delta(D)/D
(or OCV factor) on the path delay is:
sqrt(N)x0.15xD/NxD = 0.15/sqrt(N)
So the variation (std deviation) on each element is "smoothed" when there
are many elements in the path. The relationship (Normal law) above when
N is large enough (20) and/or the individual error follow the Normal law.
If N is smaller, the Student distribution should be use, but the difference
is small if N > 10.
For example a path with 25 elements shoud have an OCV of 0.15/5 = 3% while
a path with 16 elements should see 4%
Todays's commercial tools (Primetime, Pearl) apply the OCV value we specify
to entire paths without considerind the number of their elements. This is
very pessimistic and unrealistic. However, Murphy's Law is always around
and it may happen that all the elements in a path go in the same direction.
And if you have many paths in your design that are close to the required
period this probability is increased. Now we are talking about confidence
levels... I wish that tools in the future will consider these elements to
do the STA which will then be known as Statistical Timing Analysis. ;-))
- Philippe Duquennois
Philips Semiconductors Palaiseau, France
---- ---- ---- ---- ---- ---- ----
> Matt Weber writes "IBM is the only ASIC vendor I know of that requires
> this analysis". I know of at least one other, but I'm under NDA. :-)
> His discussion of common path pessimism removal was excellent, and this
> issue is critical in OCV analysis; so I'd recommend everyone read it
> through carefully and make sure they understand it.
>
> - Howard A. Landman
> Riverrock Consulting Fort Collins, CO
From: David Norris <david.norris=person company=legerity wrought qualm>
Hi John,
I'm interested in the Matt Weber OCV article referred to in Howard's reply.
Where can I find the article?
- David Norris
Legerity Austin, TX
---- ---- ---- ---- ---- ---- ----
From: Matt Weber <matt=man company=siliconlogic caught psalm>
Hi John,
I thought I'd add my Boston SNUG'02 paper and presentation to this
ongoing discussion on On-Chip Variation (OCV) in ESNUG. Those of us
doing IBM ASICs have dealt with OCV for years. I thought I add our
experiences to this thread.
My paper starts by describing what on-chip variation is, its sources,
and the problems it can cause. It shows how to enable OCV analysis in
PrimeTime and what the resulting timing reports look like. An important
part of OCV analysis is "clock reconvergence pessimism removal," and
I've included a description of what that is and why it is important.
(Just in case its usefulness is not obvious from the 43 letter PrimeTime
variable name that turns it on.)
Most static timing analysis today does not include on-chip variation
analysis. However, as clock frequencies continue to increase and process
geometries continue to decrease, I think it will become more common. I
hope my paper can help people avoid some headaches as they make that
transition.
- Matt Weber
Silicon Logic Engineering, Inc. Eau Claire, WI
[ Editor's Note: Matt's paper is #44 of DeepChip Downloads - John ]
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