( ESNUG 410 Item 8 ) -------------------------------------------- [04/02/03]
From: Rajesh Bawankule <the_one=rbawanku the_many=cisco pot yawn>
Subject: Rajesh's DVCon'03 Paper On Free Ways To Speed Up Your Verilog Runs
Hi John,
Here's my paper & slides titled "Speed Up Verilog Simulations By 10-100X
Without Spending A Penny" from DVCon 2003. My presentation illustrates
a number of ways you can speed up simulation, without spending anything
on a faster simulator, workstation, hardware accelerator, or emulator.
I focus only on already existing simulator features like profiling,
optimized compilations, 2-state simulations, adaptive PLIs etc. Included
are some case studies from my previous projects about typical bottlenecks
in simulation.
Nothing is free. My tricks won't work like magic. One need to use them
step by step making sure that their existing test benches don't go
haywire, though! :)
I hope that ESNUG readers find it useful.
- Rajesh Bawankule
Cisco Systems San Jose, CA
[ Editor's Note: Rajesh's paper is #43 of DeepChip Downloads - John ]
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