( ESNUG 410 Item 7 ) -------------------------------------------- [04/02/03]

From: Dan Joyce <captain=dan.joyce  ship=hp naught pomme>
Subject: Dan's First Place DVcon'03 Paper On How To Reduce Random Testing

Hi, John,

As per your request, here's a copy of my DVcon'03 paper.  I could have
easily titled it "Audit Your Design to Avoid the Random Testing Nightmare".
Basically it demonstrates a way to formalize the approach to corner case
testing.  The paper describes an audit of a design to try to assess the
amount of risk to corner case bugs.

Essentially, it'll teach your readers how to look at their design's
architecture to cut back the amount of random testing needed to verify it.

I've included my slides, too.  I'd love to see what your readers think
about this approach we've developed here at HP on this.

    - Dan Joyce
      Hewlett-Packard                            Austin, TX


  [ Editor's Note: Dan's paper is #42 of DeepChip Downloads  - John ]


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)