( ESNUG 410 Item 2 ) -------------------------------------------- [04/02/03]
Subject: ( ESNUG 409 #8 ) Magma, Cadence/Celestry ClockWise & Useful Skew
> In my opinion, useful skew is the way to go! My question is how many
> people are there today using useful skew in their design flow today? Am
> I one of few using useful skew or one of the many?
>
> - Simon Matthews
> Paxonet Fremont, CA
From: Jack Fishburn <soldier=jfishburn army=ieee.org>
To: Simon Matthews <cook=simon kitchen=paxonet taut fawn>
Hi Simon,
I read your posting in ESNUG about useful skew. You might want to read
http://courses.ece.uiuc.edu/ece482/Sup/Clock3/
which is my paper "Clock Skew Optimization" in IEEE Transactions On
Computers which appeared back in 1990. Wayne Dai's student, Joe Xi, then
did a PhD on clock distribution networks for useful skew, and his program
became "Clockwise" at Ultima, which was bought by Celestry, which was bought
by Cadence. Then others, such as Magma, also introduced useful skew tools.
The one thing I missed in my paper was naming it something like "useful
skew", as a result of which people kept thinking I was somehow minimizing
clock skew. But I'm pleased that it is catching on. Back in 1990 people
would look at me like I was crazy.
- Jack Fishburn
ex-Agere (Bell Labs) and looking Murray Hill, NJ
---- ---- ---- ---- ---- ---- ----
From: Simon Matthews <cook=simon kitchen=paxonet taut fawn>
To: Jack Fishburn <soldier=jfishburn army=ieee.org>
Hi, Jack,
I was aware that Ultima had a solution for useful clock skew. However, as
a point tool, I viewed it as something that only a few early adopters would
use.
Using the tool in Magma, it gives excellent results, yet, from discussions
with other Magma users, I know that some users disable the feature! I
believe they disable it because they really don't understand the concept;
or they have learned how to minimize clock skew and they don't want that
hard-earned skill to be redundant.
One person though did express the idea that useful skew could make on-chip
timing variations worse. Do you have any thoughts on this?
- Simon Matthews
Paxonet Fremont, CA
---- ---- ---- ---- ---- ---- ----
From: Jack Fishburn <soldier=jfishburn army=ieee.org>
To: Simon Matthews <cook=simon kitchen=paxonet taut fawn>
Hi, Simon,
All transistors and wires have variations in their properties that cause
timing variations. There's no reason that a useful-skew configuration will
have more, or less, timing variation than a zero-skew configuration.
However, useful-skew does give additional degrees of design freedom that can
be useful to avoid failure due to timing variation. In the example you gave
in the ESNUG posting, the short path is close to giving a hold violation if
zero skew is used:
A B C
------- ------- -------
---|D Q|-- slow logic --|D Q|-- fast logic --|D Q|---
| | | | | |
| | | | | |
clock ----|> | --|>o-|>o----|> | ----|> |
| ------- | ------- | -------
| | |
--------------------------------------------
A little bit of unintended clock delay to the destination FF "C" will cause
the path to fail by double clocking. But by supplying extra clock delay to
the middle FF "B", as in your example, the short path is given as much extra
margin against the failure.
Another way to think of it is that useful skew can be used to give extra
safety margin at the same clock period, or lower the clock period with
the same safety margin. Or you can dial any combination in between.
At any rate the static timing analyzer knows about the timing bounds in
both the data & clock networks, and will take these into account in setting
the intentional clock skew. At the end of the day, the intentional skew
circuit will be safer than the zero skew circuit. But I am painfully aware
that people who are scared will tend to reject any new technique that they
don't understand.
- Jack Fishburn
ex-Agere (Bell Labs) and looking Murray Hill, NJ
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