( ESNUG 409 Item 10 ) ------------------------------------------- [03/25/03]

Subject: ( ESNUG 347 #1 ) Cliff Adds #1 Delays To His Non-Blocking Paper

From: Cliff Cummings <england=sunburst-design shot gone  london=cliffc>

Hi, John -

Back in ESNUG 347 #1, I sent you my first place paper from SNUG'00 on Non-
Blocking Assignments in Verilog.  I've updated that paper with a detailed
examination of performance data related to adding #1 delays and removing
them.  This updated paper shows how to add them if you must and it shows
why they might be needed for mixed RTL-gate level simulations.  The new
paper also shows why the VHDL coding style of making blocking assignments
followed by NBA's (variable assignments followed by signal assignments) is
a bad idea, leading to confusion during debug and is unnecessary in
Verilog -- my VHDL jab for the paper.  ;-)

    - Cliff Cummings
      Sunburst Design, Inc.                      Beaverton, OR


 [ Editor's Note: Cliff's new paper is #40 of DeepChip Downloads  - John ]