( ESNUG 408 Item 3 ) -------------------------------------------- [03/13/03]
From: John Cooley <isp=theworld taut bon account=jcooley>
Subject: Three Anonymous Customers Review The Tharas Hammer Accelerator
Hi, all,
Here's what I got when I surveyed some Tharas Hammer users last week.
- John Cooley
the ESNUG guy Holliston, MA
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From: [ Bachelor Number One ]
Hi John -
Here's my feedback on the Tharas Hammer. Please note that my information is
somewhat dated as the last version of the Hammer compiler that I used was
from about November 2001. There have most likely been updates since then.
I'll have to request the anonymous handling.
We first engaged with Tharas about August of 2000. At that time the Hammer
Accelerator still had a few hardware bugs. Also at that time, the Hammer
would not fit our complete design and it had some parsing problems with some
of our source code and there were some problems with using our ASIC vendor's
libraries (the "source code" of the design had some instantiated gates.)
Also at that time we were using VCS (maybe version 5 or so) as our main
simulator and it was taking 8 to 12 hours of VCS sim time or more to get
results from any given simulation. With a one day turn time for sims, we
had a great desire to use acceleration.
By about late Dec 2000, the Tharas folks had solved all of the problems that
had prevented the use of the Hammer and we could actually start using the
Hammer for simulations in our regression flow. Although the Hammer was
really designed for RTL acceleration, the Tharas software personnel did a
major rework of their Hammer compiler code to allow the use of the
instantiated gates. In this time frame, the compile for a Tharas simulation
on our device was taking over 12 hours, but we were seeing a 20 to 25 times
acceleration compared with VCS 4-state no-timing sims.
At that point, the management of our ASIC group decided to purchase the
Hammer accelerator. Throughout the next year or so, the Tharas software
group continued to make some major improvements: compile time down to about
1 hour, compile process size from 3.8 gig to about 2.2 gig, incremental
compile of the testbench part of the simulation. (A Tharas simulation has
2 parts, the accelerated part that is run on the Hammer hardware, typically
the DUT code, but can include some test bench constructs, and a VCS
co-simulation that runs in parallel on the host workstation).
Also during that time development on VCS continued and I think it was VCS
6.1.1 where the run time of VCS sims dropped by about 40% to 50% for our
design. Also we were making improvements to our simulation strategy to cut
the VCS sim time down (using PLI's to nearly instantly program registers
as an example.)
Tharas strengths:
1. Regression flow nearly the same as VCS flow.
2. Simulation results agree very well with VCS for our design.
3. The Tharas compiler can be tweaked to address certain
design constructs.
Tharas weaknesses: (you might pass these issues by Tharas as these issues
may have been addressed by this time)
1. During our use it was hard to use the Hammer for waveform
debug for 2 reasons:
A. Our design just fit into the Hammer and enabling waveform
dumping would not allow the design to completely fit.
B. There was a pretty severe performance hit when dumping
waveforms (VCS also has this hit but by a smaller factor).
2. Acceleration varies depending on the design and on the test
bench architecture. It may be difficult to estimate the
acceleration without actually trying the device.
I have only used an IKOS simulator for running coverage tests in the early
90's, so I can't really comment much on competitors. I did observe some of
the evaluation process of the AXIS acceleration scheme and it seemed much
more expensive and harder to use.
The good part was how hard the Tharas people worked to make the Hammer work
for us. They really tried to address all issues whether it was a deficiency
of the device or whether I was asking for an enhancement.
- [ Bachelor Number One ]
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From: [ Bachelor Number Two ]
Hi John,
I would like you to keep my name and my company's name to be anonymous.
Here are my impressions.
Hammer strengths:
1) For our 8 million gate ASIC at RTL level pushed into the box, we get
10-14x performance improvement over the 900 MHz Solaris machine.
2) The same ASIC at gate level, gives us 40x+ performance improvement
over the 900 MHz Solaris machine.
3) Hammer is easy to use
4) Though Tharas is a startup, we have received superior customer service
like we expect from established companies.
Hammer weakness:
1) Now that I can run VCS 6.2 on Linux boxes and I find 2-3x performance
improvement on 2.4 GHz Dell Linux Servers over the 900 MHz Solaris
machine, the price of Hammer, as long as it is connected to Sun
Solaris, does not justify its peformance over Linux machines. Their
price will be more justified, if I am able to connect Hammer to a
Linux machine and run my simulation. Tharas is working on this now.
2) Sometimes, the Hammer gets hung in the middle of the simulation and we
need to get Tharas involved to resolve the issues. Given the superior
service they provide, this becomes a non-issue at most cases.
My Wishlist for Hammer:
1) For an ASIC of our size, we dont know yet whether we will be able to
run gate sim with SDF or not. It will be a breakthrough in the
industry if we can run gate sim with SDF using Hammer.
2) Taking the testbench constructs in C/C++/Verilog into the box so
that the hammer can run with minimal dependance on the host machine.
Concern:
Being a startup, how long will they keep on providing the excellent
customer service to us?
Overall impression:
Their strengths outweight their weaknesses. We are glad to have Hammer in
our ASIC simulation environment.
- [ Bachelor Number Two ]
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From: [ Bachelor Number Three ]
Hi, John,
I will try to answer the questions you've asked about Tharas. Over the past
5 months, I had not worked with Hammer machines because of other
assignments. Please allow some degree of inaccuracy.
Here is my humble comments. Must be anon.
1. What are its strengths?
- Larger than 10x simulation throughput over VCS (in our chip.)
- Hammer opens up the possibilities for system level simulation
with multiple instances in RTL form in a reasonbale cost.
2. What are its weaknesses?
- Reliance of proprietary ASIC parallel processors. The advantage of
Hammer's sim throughput is diminishing as Sun or Linux workstation's
computing power keep on advancing.
Our concern is if Tharas can keep up the pace.
- Hammer seems to have more compiler switches than I would prefer.
In my memory, we had to turn on one switch otherwise Hammer
can not simulate correctly.
- For our design it seems require more memory (than VCS) in run time.
3. How does it compare to Quickturn, Mentor, Aptix, and its others?
compared to Quickturn: Hammer is easier, cheaper to maintain.
Hammer's re-compilation is much faster
than Quickturn's remapping.
compared to Aptix: Hammer is less expensive. I do not have Aptix
performance data.
Mentor: no data.
4. What bit of hard earned wisdom did you learn after buying Hammer that
you had wished someone had told you about before you bought Hammer?
- Before the purchase, we only used a small set of test patterns to
check Hammer's performance and we gave Tharas a performance goal.
Tharas assigned 1 full time engineer, we assign a half time engineer.
After they met the initial performance goal and we agreed to purchase
Hammer, we discovered that Tharas may have "optimized out", through a
compiler switch, part of RTL which are not exercised by these patterns.
So the performance data before the purchase decision may be misleading.
5. What good part of Hammer surprised you?
- Last summer, we ported a pre-released RTL to Hammer and used a less
complete verification suite designers were using. We flushed out
several RTL bugs which had slipped through VCS simulations. If we
would have a regression suite with full coverage then we might catch
those bugs in VCS.
Thanks for the opportunity for expressing my comments.
- [ Bachelor Number Three ]
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