( ESNUG 407 Item 10 ) ------------------------------------------- [02/26/03]
Subject: ( ESNUG 395 #11 ) Denali IP For DDR/SDRAM Interfacing And MMU's
> We are looking for IP in the field of DDR/SDRAM memory interface and MMU.
> Do you know of anyone in this business?
>
> - Nir Sever
> Zoran Israel
From: Mike McKeon <celtics=mike nba=denali knot john>
Hello John,
We offer customizable memory controller IP for DDR SDRAM, FCRAM, RLDRAM, and
SDR/DDR SDRAM applications. Each core is customized to match the exact
application for the ASIC in order to achieve 100% bus utilization. Our
Databahn customization process is accessed via an online interface at the
http://www.eMemory.com site. Our browser-based interface creates a machine
readable specification file (SOMA) that drives the generation of the RTL
from a single Verilog code base, which can then be simulated online to
validate performance. Once your performance targets are met, verification
routines, synthesis scripts, static timing scripts, and documentation are
generated.
Our Databahn IP is library independent and covers solutions from .18 um to
.11 um technologies in DRAM device frequencies from 100-250 MHz (200-500 MHz
data rate.) We have first silicon with 5 Databahn cores in 3 different ASIC
processes. There are currently over 25 Databahn licensees with controllers
in active development.
- Mike McKeon
Denali Palo Alto, CA
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