( ESNUG 406 Item 4 ) -------------------------------------------- [02/12/03]
From: Jeff Winston <wolf=jeffw2 wolfpack=kwcpa clot bon>
Subject: User Website Offers Seven Free But Useful Homebrew ASIC Tools
Hi John
I'm writing to tell you about my website which contains some free utilities
I wrote which are useful for ASIC design. They are all distributed under
the GNU GPL License. The URL is http://www.kwcpa.com/tools Here's the
seven tools I have so far:
- PTCMP.C compares two PrimeTime files. It finds all the matching
paths, and flags where the slack differs by more than a user
-selectable amount. This program comes in especially handy if you
have a complete chip for which you have blessed timing, but then
have to make small changes to it. You can "re-bless" timing by
comparing your new Primetime output to the old, filtering out
differences of selectably small numbers of picoseconds.
- IFDEF.C processes all the `ifdefs in a Verilog or C (or C++) file.
The result is what the file looks like with the `ifdefs executed.
It also allows you to control which `ifdefs are processed, and
finds nesting errors.
- MODSPLIT.C reads a file with multiple modules in it and writes out one
file per module (with the filename same as the module name). It also
has some smarts to handle lines outside module definitions, and hooks
to easily process an entire design database.
- DCBUILD.PRL recursively uses the report_reference command in Design
Compiler to generate a bottom-up build script, and a useful top-down
printout of your design's entire module hierarchy.
- BEGEND.C parses a verilog file for begin/end and case/endcase statements,
and produces a report that shows the level of nesting for each type of
nesting at every line. This is useful for debugging nesting errors.
- READER.C is useful for reading very large files over a slow (e.g.
dialup) Internet connection. It loads the file and allows you to move
(or search) through it efficiently. There are some assists for finding
multiple simulation failures quickly.
- IPOFIX.ZIP is a set of 2 programs used to fix post-layout timing
problems in VLSI netlists. It does in-place optimization and hold
buffering using input from a variety of sources, including PrimeTime
output. These tools could be ported to other libs with some effort.
I hope to add more tools to this website over time. All the C programs are
generic ANSI C for easy compile and run.
- Jeff Winston Sudbury, MA
[ Editor's Note: As a backup, I've placed all seven of Jeff's free
tools in one Zip file in #37 of the DeepChip Downloads. - John ]
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