( ESNUG 405 Item 11 ) -------------------------------------------- [01/29/03]
Subject: Steve Golson Cites Verplex' Anti-Formality Disinformation Campaign
> "One of the main reasons customers continued to use Design Verifyer
> instead of Formality is that it is independently developed technology,"
> Dino Caparossi of Verplex marketing said. "They don't have to worry that
> their formal tool is making the same mistake as their synthesis tool.
> That's also one of the primary reasons that customers are still choosing
> Conformal over Formality, aside from our continued winning of the
> benchmarks. With this decision, Synopsys has essentially killed off their
> only piece of independently developed formal technology, which should make
> our job of migrating the remaining Design Verifyer customers even easier."
>
> - from EE Times 01/17/03 http://www.eedesign.com/news/OEG20030117S0027
From: Steve Golson <termite=sgolson house=trilobyte shot pawn>
Oh please, John.
Dino's comments makes me want to repeat Ronald Reagan's famous comment of
"There you go again!" I've heard this sort of FUD (Fear, Uncertainty,
Doubt) about Formality for almost 5 years now. (See ESNUG 282 #10) Back
then it was Chrysalis who said it, trying to boost support for their
pioneering tool Design VERIFYer.
Even less than a year ago (ESNUG 394 #4) users were *still* worried about
the same thing: "Formality and Design Compiler have the same engine! You
can't trust it! Aaaaah!" Well, actually, there was a kernel of truth to
this, but it's old news, and no longer relevant.
Come 'round my children, and I'll tell you a story...
Originally, Formality and Design Compiler *did* use the same front end: HDL
Compiler. Thus if there was a bug in HDL Compiler then it was possible that
during the initial parsing of the Verilog code, both Design Compiler and
Formality would get the same *wrong* answer. And your verification tool
would be useless. I don't know if this ever actually happened, but it was
possible.
Users pointed this out (ESNUG 283 #1), and Synopsys rapidly moved to fix the
problem. They bought a front-end RTL compiler called "Concorde" which was
developed independently by Interra Systems (http://www.InterraSystems.com);
so ever since 1999 or so for Verilog (and fall 2002 for VHDL) the Formality
front-end has been independent of Design Compiler.
Note the back end has always been different. It had to be. Formality uses
a four-state synthesis engine (1,0,X,Z) while Design Compiler collapses all
the X unknowns very early in the synthesis process to ones and zeros.
However, HDL Compiler is still there! If you use the "-hdlc" switch on
read_verilog then Formality will use HDL Compiler rather than the Interra
RTL engine. So you get the best of both: if one front end has a bug, you
can switch to the other. Can Verplex do that?
Furthermore, I think that having *some* code in common is a benefit for
synthesis and formal verification tools. For example, if you have a
schematic display capability, isn't it useful for *both* tools to have the
same GUI? This consistency makes it easier to learn the tool. Also it's
nice that Formality can use the same command line arguments as VCS. And I
think it's great that Formality can read .db library files. (Yes, I verify
the .db against the simulation files first!)
A large company like Synopsys has many opportunities to intelligently share
code across a diverse product line. For example, the Verilog library reader
in Formality is the same one used by TetraMAX. If there is a problem, you
have a wider user base who can catch it. Test cases are important, and
nasty snippets of Verilog code can be used to wring out many different
tools. (Actually I think this is one of the biggest benefits that Synopsys
got when it acquired Design VERIFYer -- all those test cases that Chrysalis
/Avanti had developed over the years.)
If Verplex wins in my customer benchmarks, that's great! I'll buy the tool!
But I don't think that being "independent of Synopsys" is a legitimate
reason to buy Verplex over Formality.
To the Verplex marketing folks out there: Give up the FUD. That dog won't
hunt any more. And don't belittle your competitor's products. Let us users
do that for you!
- Steve Golson
Trilobyte Systems Carlisle, MA
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( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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