( ESNUG 402 Item 7 ) --------------------------------------------- [10/23/02]
From: Pallab Chatterjee <pallabc@siliconmap.net>
Subject: A Report On What Went On At Last Month's Magma User Group Meeting
Hi, John,
Here is what I saw at last month's Magma users group meeting. First, the
numbers:
Overall attendance 80 people
Total # Magma Technical Papers 7
Total # Magma Tutorials 6
The conference was a pretty good show - much more technical than I
expected. The papers were similarly themed as "the Magma software did not
work as well as we planned - BUT their apps people and R&D people worked
with us and we not only SOLVED the problem, but developed a repeatable
solution for future projects". This is actually what you want for a user
group. I was just surprised at the level of detail and positive attitude
of the audience. (I am used to the typical Avanti Aurora audience which
was either passive or ticked off).
The two big Magma sessions were the Magma tutorials:
"Beyond timing constraints - tools for timing correctness" by Tim Burks
and
"Maximizing Blast Fusion for Runtime/Capacity/QOR" by Kam Kittrell.
Tim's tutorial went in depth on how to properly import a library (best and
worst case info) into the Magma environment and the new GUI based debug on
timing analysis including false and multicycle paths and full net
details. This was one of many discussion on the concept of "usefull
slack" that ran through the conference. Several customers indicated that
Magma was the only one really doing useful slack properly although there
was heated debate about the term properly.
This tutorial also went through two important areas - how to describe the
clocks for both flat and hierarchical mode for skew calculation and the
layout trace commands. The clock discussion was primarily verbal against
some schematic examples - there was no TCL code or command line examples
given to accompany it but lots of user notes were taken.
The highlight of this talk were the new command descriptions for the layout
trace commands which is the GUI for matching timing information to the
layout nets and placement. The new commands reviewed were:
ui layout trace create <conn>
ui layout trace add <conn> <trace> <from> <to>
ui layout trace path <conn> <trace> <pin 1> <pin 2> ... <pin n>
ui layout trace display <conn> <trace>
( -flyline, -wire_all, -wire_arc, -wire_bbox options )
ui layout trace visible <conn> <trace> -on/-off
ui layout trace delete <conn> <trace>
ui layout trace clear <conn> <trace>
These commands have existed in the code for a while but most users did not
know they were added.
This tutorial followed keynote comments, a user paper and several highlights
in other user papers about the importance of the library validation (.lib vs
SPICE) for the IP blocks in order to have Magma return a "real" timing
closed answer. Due to the fully integrated nature of the tool, the BlastXXX
flow has a major garbage in - garbage out problem. All the Magma tools are
predicated on the assumption that the library description data is CORRECT
and everything is self consistent from that point. If you have bad or out
of synch characterization of IP blocks and standard cell libraries the Magma
tools will NOT give you an answer that correlates to post layout extracted
SPICE rather is correlates ONLY to the input timing data given.
Kam's tutorial on maximizing runtime focused a lot on the changes between
the current Magma releases and V 3.2 that is released in October. The main
feature of the new Magma release is the increase in capacity to about 2 M
placeable instances per level of hierarchy under the standard 32-bit Linux
kernel. The previous versions were stuck at about 500 K placeable objects
due to Red Hat's limit of 3 Gb max address space (or 3.5 Gb with some OS
patches) and the old addressing scheme on 32 bit. The 3.5Gb problem still
remains, but Magma tweaked their mapping scheme so they can get the larger
design sized through.
The tutorial reviewed a number of memory management tricks and utilities
that are applicable for the current version 3.1 release. Two best return
memory management tricks that were reviewed were:
1. Pruning the unused memory components this is done with the command:
data prune library $l <pad, pad_filler, pad_corner, macro>
2. Blast Fusion allocates memory dynamically, the dynamic memory
allocation can produce memory fragmentation of >20%, in order to
increase the memory available the following procedure should be
followed:
* save volcano after major steps
* exit, restart tool
* reload volcano and continue
The other Magma non-GUI related hint provided was with respect to the clock
router. In order to get a reduced insertion delay - the clock should be
routed with 2x width and 2x space. This is done by the following sequence:
- rule net nondefault <2x spacing and width per layer>
- force net nondefault <clock root net>
- run route clock" within fix clock will propagate the non-default
rule to children
The other tutorials were (A) Hierarchical design using Blast Plan and Blast
Fusion and (B) using Blast Noise for Noise Avoidance.
There was a minor snafu on the R&D Chat sessions. Since it was a first
year conference and the participation level of the audience was not known,
the R&D people were told to present some questions to kick off the
discussion. This prepared material was a bit much in length the two chat
sessions became additional tutorials. These were on Virtual Prototyping
and Sign-off Verification.
The user papers were pretty good for a first year conference. The only
fast one that slipped in was from Forte Designs. They presented a 90%
marketing content piece on their products and they presenter was the
VP of Mktg. The attendees were cordial to them, but it is generally NOT
an acceptable practice to do a sales piece in a technical conference.
There are so few "technical engineering" venues out there vs sales and/or
marketing venues it really shows the desperate and amateurish nature
of the vendor to try and force the engineers to listen. This generally
results in a negative impression of the vendor rather than any positive
information or spin that could theoretically happen. Other tech
conferences should be on alert to watch for this sort of activity.
There were three user papers that were noteworthy from this conference. Two
of them can be posted on DeepChip for people to review, we are waiting for
the OK before the ST paper gets posted. The three papers were: ST
Microelectronics - SOC Hierarchical flow with BlastChip, GDA Technology -
Methodology for Reducing the Signal Integrity Effect and Optimizing the
Time to Tapeout, and SiliconMap - An Optimal Timing Closure Methodology for
Blast Chip based on Automated Library Characterization. ST Micro is a
customer of Magma. GDA Technology and SiliconMap are both design centers
certified to run Magma tools for customer projects - however, neither group
receives compensation or referrals from Magma.
The ST paper went through a lot of details on their flow conversion using a
traditional LEF/DEF interface and module separation. The most interesting
portion of their talk and paper was the way they handled multiple power
supplies in the Magma tool. The other tools on the market follow the
convention of the power router handles the digital core as a power global
and other supplies are best dealt with as localized "signals" rather than
power supplies. This does not work for the Magma flow as the Power signals
are routed with a different width/spacing than regular signals and the IR
drop avoidance feature only works on power nets.
The ST solution involves several TCL scripts to identify and order power
pads, place the new pads, and verify that the new multi-power rings are
setup properly with avoidance in the Magma environment rather than waiting
for verification n Calibre.
This is an interesting solution as the SilconMap recommended work around
for the multi-power problem is to localize the segmented power rails in
stand alone modules. These isolated power rails are then hierarchically
route the power pads WITH the logic for the module. At the next level of
the hierarchy these pads are no-longer propagated.
The GDA Technology paper dealt with Signal Integrity issues in the design.
It focused on shielding of nets and the effect of the Victim/Aggressor net
analysis in the Magma tools to resolve the problems in the deisgn. The
features used in this analysis are all in the current release from Magma
and other than being easier to support (integrated launch and result
analysis) and as complete as standalone analysis with Simplex or Synopsys
products. This paper will be available on the DeepChip downloads site.
SiliconMap presented a paper about library modeling and an automated
routine for dowloading, running and analyzing revised device level library
data and then creating the necessary timing, power, and SI view for these
libraries and importing them into the Magma flow. The highly integrated
architecture of the tool can lead long loops for timing closure if the STA
results, based on the .lib information, and the results of device level
simulation from post layout extraction are not based on the same revision
of modeling information. When this data is out of sync, then the Magma
tools tend to return results that are oversized and over powered based on
silicon correlation. With this new synchronized data, then the results are
typically smaller and lower power than you would get from traditional post
layout analysis APR flows. This paper and powerpoint will also be available
on the DeepChip downloads site.
As a summary. For a first year conference it was a good show. There was a
surprisingly active dialogue between the presenters and audience which
seemed out of character with the historically quiet nature of the Magma
client base. If there are any Magma Users who missed the conference and
would like a complete copy of the proceedings and Keynotes, please contact
your Magma Sales person to get a copy on CD.
- Pallab Chatterjee
SiliconMap, LLC. Livermore, CA
[ Editor's Note: I'll have the 3 papers Pallab mentioned up on the
DeepChip downloads section by the end of the week. - John ]
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