( ESNUG 402 Item 2 ) --------------------------------------------- [10/23/02]
Subject: Newbies Discuss Cadence Silicon Ensemble / Virtuoso / DW Basics
> I am a new user of Silicon Ensemble. I read up the documentation on it,
> but still had a few basic questions about it. I am trying to see if I
> could use just the router to route a placed design of mine. Could someone
> tell me if I still need to create both the LEF and DEF files, if so, is it
> possible to create these from the layout (having the design to be routed)
> and the technology file respectively?
>
> Can I do away with the timing and the constraints file, because all my
> routing will be very simple without any timing goals? What would be the
> essential files for a route to be performed in my case?
>
> - S. Hemanth
From: Regis Caillet <regis.caillet@dspfactory.ch>
Yes, you can use wroute in stand alone. You give it the LEF, DEF & wroute.cfg.
LEF gives it all information on the process technology, cells, memories and
other stuff. DEF gives the placement of your cells, memories, pad, size of
floorplan, the ring of alimentation and the netlist. Wroute.cfg indicates to
wroute where to find the files, how you want to route and other stuff.
How did you create your floorplan, placement ?!
- Regis Caillet
DSP Factory Switzerland
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From: S. Hemanth <shemanthk@yahoo.com>
Hi Regis,
Regarding your question about my floorplan or placement, depending on the
circuit, the positions of the various components are fixed and I draw this
floorplan or placement out in Virtuoso. Then I somehow want to be able to
use this for routing. I plan to use SE wroute in a synthesis flow with
different sizes for the components, with the placement being fixed. Is it
possible not to generate the LEF and DEF files everytime, but just do it
once and use them with parameterized sizes? Also, do you know if I can
automatically produce the LEF file from the technology file?
- S. Hemanth
---- ---- ---- ---- ---- ---- ----
From: Regis Caillet <regis.caillet@dspfactory.ch>
To produce your LEF file, you can read all your individual LEF files into SE
and export it into one big file out. SE exports a LEF file, but it is in
binary, not ASCII that you can read.
import lef filename "directory/name_tech_file.lef" ; [always the first]
import lef filename "directory/name_cells_file.lef" ; [as you want th order
for the others one]
import lef filename "directory/name_memories_file.lef" ;
import lef filename "directory/name_pads_file.lef" ;
...
Why don't you just make your floorplan with SE ?!
- Regis Caillet
DSP Factory Switzerland
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From: Shrirang Yardi <syardi@hotmail.com>
Hi,
I am also a new user to Cadence SE. I read the documentation and found that
one needs to have a gds2.map file to export your layout from SE to Virtuoso.
I am not able to find the gds2.map file in my Cadence installation. Is this
file supposed to be provided by the vendor?
- Shrirang Yardi
---- ---- ---- ---- ---- ---- ----
From: Muzaffer Kal <kal@dspia.com>
If you have the technology information from your foundry you should be able
to generate the gds2.map file yourself. Basically open the library LEF
file, look at the header to see the names of metals and vias then find the
process manual to see which layer numbers they use for those layers and put
them in the gds2.map.
- Muzaffer Kal
DSPIA Inc.
---- ---- ---- ---- ---- ---- ----
From: Han Speek <Han.Speek@philips.com>
Hi, Yardi,
The gds2.map file you need for this is technology-dependent, so if it's at
all provided it should come from the foundry (assuming you're using a design
kit, it should be part of that). But there's a good chance you'll have to
make your own. Have a look at the stream layers section of the tech file
for the info about how layer names and purposes map to numbers.
But why are you using gds2 anyway to take the design back to Virtuoso?
Normally the DEF format is used for this, and you can write that out without
any additional technology file. Then in Virtuoso, do an "Import DEF", and
you'll end up with a layout that has the cell abstracts. Then, from the top
menu bar, do a "Floorplan -> Replace view" to swap the layouts in for the
abstracts (don't forget to select "all" !), and finally select "Layout" from
the Tools menu to get the normal layout editor menus back.
Then, if gds2 is required anyway, you can now simply stream out the layout
view using the CIW Export Stream functionality.
- Han Speek
Philips
---- ---- ---- ---- ---- ---- ----
From: Regis Caillet <regis.caillet@dspfactory.ch>
Yardi, you should see on cadence web site:
http://sourcelink.cadence.com/docs/db/kdb/1999/Dec/1836672.html
It's in SourceLink.
- Regis Caillet
DSP Factory Switzerland
---- ---- ---- ---- ---- ---- ----
From: Dmitriy Shurin <shurin@bgumail.bgu.ac.il>
Hi,
I have a digital library that includes all the necessary files for working
with SE and Synopsys, but the layout cellviews for basic cells were not
supplied. After I was done with SE, I tried to transfer the result into
a layout editor, but since my layout view is absent, I get a huge number of
warnings and (of course) no layout. The problem is that not only the layout
of basic cells is absent, but the *routing* that was made by SE is also
missing! Is it possible that the layer/purpose of the routing made by SE
is metalX/net and not metalX/drawing or is there another reason my routing
is also absent in LE?
- Dmitriy Shurin
Ben Gurion University Israel
---- ---- ---- ---- ---- ---- ----
From: Paul Fields <psf2001uk@yahoo.com>
Hello Dmitriy,
There should be a GDS II stream-map file that SE reads when it writes-out
the GDS II data from the routed design. Maybe you already got this with the
library, or maybe you will need to write this yourself.
You should also check that this layer mapping (e.g. metal1 = 14) matches the
technology file and mapping file you use in your layout editor. If these
are consistent, at least you will be able to see all of the metal and via
layers created by SE.
I don't know if you are using the Cadence Virtuoso layout editor. If you
are, what you could do is to make a libary called myLib, attached to the
technology file for your process, and stream-in the GDS II of your library
cells into here. If you have RAMs or other blocks, you might want to make
other libraries for these. Then, stream the GDS II file written by SE into
another library, and reference the libraries myLib, myRAM, etc., when you
stream-in. In the File/Import/Stream.../Options form, set:
Retain Reference Library (No Merge) - YES
Reference library order myLib myRAM myADC
Use a space-seperated or comma-seperated list.
OK this, then OK stream-in form - PIPO.LOG will show:
(inv1/layout) - (referenced, but not defined, no data created)
(dffr/layout) - (referenced, but not defined, no data created)
When streaming-out your design, to make a "full" GDS II file, do not select
"Retain Reference Library (No Merge) - then stream-out will write-out ALL
cells.
- Paul Fields
---- ---- ---- ---- ---- ---- ----
From: Alistair McEwan <alistair@robots.ox.ac.uk>
Hi,
What is a clock root net (or pin)? SE reports that it cannot find one in my
design when I try to run clockroute. Is this the recommended way to route
the clock or should WROUTE be used just selecting the clock net?
I used PRflattern to generate an autolayout of my design and the
FloorplanP&R|Silicon Ensemble to set the vdd! and gnd! nets special. Then
I exported to a DEF. There is a line in the macro file provided by the
fab which states "change net '<Netname>' use clock ;" SE didn't understand
this so I edited the DEF in a text editor and added the line + USE CLOCK
to the CLK net section. I don't have a verilog model of my design either
so I disabled all the verilog parts of the macro file. The CTGen section
works fine. I've given the slew rate, delay and waveform constraints for
the root_iopin 'clk' in the ctgen constraint file.
But as soon as the macro file reaches clockroute it complains that it cannot
find any root clock nets or pins. I read a very old post that warned that
clockroute is not the router of choice, but rather to use WROUTE just on the
clock net. This just seems to treat my clock net as a regular signal net
which is not acceptable as the path width is minimum and therefore will not
be able to carry the required current.
Every tutorial I've read doesn't seem to cover clock generation. Does
anyone know of one that does?
- Alistair McEwan
Oxford University England
---- ---- ---- ---- ---- ---- ----
From: Regis Caillet <regis.caillet@dspfactory.ch>
To route your clock with Wroute, you need to change this variable before you
actually lauch wroute itself:
SET VAR WROUTE.SELECTNET.FIRST true ; -- indicates to route a categorie
of nets before the others
SET VAR WROUTE.SELECTENETS "@clock" ; -- which nets or type of nets to
route in first
When you applied CTGen on your design, at the end it propose to load the
change of the netlist (with the gui). If you use CTGen in stand alone, you
need to import the change manually after CTGen.
- Regis Caillet
DSP Factory Switzerland
---- ---- ---- ---- ---- ---- ----
From: Chenbo Liu <philewar@icc.sh.cn>
Hi, folks,
For saving the cost in mask, one customer choose to route their design with
one metal layer in Silicon Ensemble. It seems impossible unless you do it
by hand. But I'm not sure and turn to you for help. Any suggestions?
- Chenbo Liu
Bentium, Ltd. China
---- ---- ---- ---- ---- ---- ----
From: Han Speek <Han.Speek@philips.com>
Hi,
I don't think that can really be done. You "need" a second routing layer,
even if only to make crossings over your power lines. You could use
polysilicon as the second routing layer - but SE isn't really very good at
that. :-( And generating proper abstracts for routing with poly isn't
quite trivial either. In fact, I'm not convinced that it can even be
done with Cadence's current routing tools.
So to summarize:
1) you need a second routing layer to make crossings in your routing
and
2) you have to pick that second layer with the tool's capabilities in
mind.
My choice would be to go for a second metal layer.
- Han Speek
Philips
---- ---- ---- ---- ---- ---- ----
From: Paul Fields <psf2001uk@yahoo.com>
Generally, you would use poly as the "second" layer. Obviously, given the
much larger sheet rho of poly (maybe 30 Ohms per square, vs. 30 milli-Ohms
per square for metal), you need to be very careful to avoid the use of poly
in clock lines (maybe route the clocks first so they can use metal wherever
they go, or hand-wire in a dedicated metal clock wire in each channel, and
tap it directly into each flop clock input).
SE certainly **used** to support 1.5 routing layers (i.e. 1 metal + 1 poly)
in the technology set-up you could raise the cost of using poly so that it
was only used for short hops. You would use metal to route along the
channels, and then poly to cross between different tracks in the routing
channel, and hook up to cell inputs/outputs.
This was pretty much standard practice with the older (cheaper) processes in
the 1 to 3+ micron size. Blocks were much smaller of course, so you could
manually inspect clocks and critical paths after routing.
I used to dream of 2 layers of metal....
- Paul Fields
---- ---- ---- ---- ---- ---- ----
From: Chenbo Liu <philewar@icc.sh.cn>
My design is about several K gate counts, and my question is if it's a must
to ungroup all Synopsys DesignWare components before going into SE. Or can
SE handle it all the same?
- Chenbo Liu
Bentium, Ltd. China
---- ---- ---- ---- ---- ---- ----
From: Arvin Patel <apatel@chello.no>
Hi Chenbo
There should be no need to ungroup DesignWare components before reading the
netlist into SE. SE flattens the design anyway after it has been read in.
However you might want to ungroup the DesignWare components anyway, not
because SE needs it, but because Design Compiler can optimise the logic
further to possibly produce a better result after ungrouping the DesignWare
(DW). Note that this means that information about DW is lost and any
optimisations by changing DW components architectures is not possible.
- Arvin Patel
Chello Broadband Norway
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