( ESNUG 393 Item 3 ) --------------------------------------------- [04/25/02]
Subject: ( ESNUG 390 #6 ) Ericsson Didn't Do A Synplicity ASIC Benchmark!
> Although my own stock in Synplicity got temporarily hammered when your
> latest article about them was published ...
>
> - Bill Cox
> VI ASIC
From: Gayatri Japa <gayatri.japa@indiatimes.com>
Dear John,
Mike Dini advertizes his services on the Synplicity web page. Bill Cox
admits he owns Synplicity stock. You should screen your emails better.
- Gayatri Japa
India Times
---- ---- ---- ---- ---- ---- ----
From: Mike Djamoos <MDjamoos@WhiteRockNetworks.com>
Hi, John,
We use Synopsys Design Compiler for ASIC synthesis. While Synplicity has
done a great job of addressing the specific needs of the FPGA community,
we decided to stay with the tool with which we are most familiar when
designing ASICs.
- Mike D'Jamoos
White Rock Networks
---- ---- ---- ---- ---- ---- ----
> One of our designs is highly parameterized using generic and loop
> statements. We also use 3-dimensional arrays. The Synopsys software
> needs more than 30 hours for the synthesis! In contrast the Synplify
> ASIC software needs only 40 minutes and achieves results of the same
> quality than the Synopsys software. The setup of the Synopsys
> synthesis environment took more than a week. The results from Synplify
> ASIC were achieved within a day.
>
> So a clear statement from my side is that Synplicity software is far
> more easy to handle and more efficient than the Synposys software!
>
> - Juergen Dennerlein
> Ericsson Eurolab Deutschland GmbH Nuremberg, Germany
From: Juergen Dennerlein <Juergen.Dennerlein@eed.ericsson.se>
Hi John,
After having talked to several designers it seems to me that my e-mail in
ESNUG 390 #6 seems to be misunderstood. The word "benchmark" I used implies
too much. Better would have been to say "we had some interesting results
after quick tests" because we didn't perform a benchmark. With respect to
the runtimes we did experience 30 hours with Design Compiler. The 40
minute Synplify ASIC runtime was reported to us by the Synplicity Munich
office. We provided Synplicity the RTL code and they reported us back the
runtimes. They reported they achieved timing within a day! Up to now we
haven't checked the netlist results yet.
When I wrote I didn't know that Synopsys already had taken action to tackle
the problems we encountered with our parameterized design. It was about 12
days ago when I got the info that Synopsys already had brought down the
synthesis run time to an acceptible value of 5 hours by coding style changes
and usage of special DC attributes. Furthermore I didn't know that Synopsys
already had commited them to fix these problems in the next Design Compiler
release. Nonetheless, I would like to point out that it's not acceptible
that designers have to adapt to a tool specific coding style or that they have
to know such special constraints. An easy to handle tool should take over
those tasks in order to free the designer for real design work!
I hope this email clarifies what people were questioning.
- Juergen Dennerlein
Ericsson Eurolab Deutschland GmbH Nuremberg, Germany
[ Editor's Note: I want to thank Juergen for setting the record straight
here. In my book, it's NOT a benchmark when the Synplicity people run
the tool and report back their "results". This is not an anti-
Synplicity sentiment. I distrust *any* benchmark data that comes from
*any* EDA vendor. I've been lied to too many times. In re-reading
ESNUG 390 #6, I also noticed that Frank de Bont of Arcobel had some
benchmark numbers in his letter. I will be investigating if Arcobel
had actually used a copy of Synplify ASIC in house or not. - John ]
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