( ESNUG 393 Item 2 ) --------------------------------------------- [04/25/02]

From: Paul Zimmer <pzimmer@cisco.com>
Subject: Does Your ASIC Vendor Make You Time For A 12% On-Chip Variation?

Hi, John,

Our current ASIC vendor is having us do timing analysis with an on-chip
variation of 12%, applied to both cell delays and interconnect delays.

This makes certain kinds of timing very difficult to pass.  For example,
using a PLL to zero out a 5 ns insertion delay requires a 5ns feedback
path.  But 12% variation between the two is 600 ps, which is a big chunk
of time these days.  Source-synchronous interfaces have similar problems.

How realistic is this sort of thing?  Has anyone done a paper on this?

    - Paul Zimmer
      Cisco Systems