( ESNUG 392 Item 2 ) --------------------------------------------- [04/18/02]
Subject: Synopsys R&D Q&A To The SNUG'02 Design Compiler Tutorial (Day 2)
1. Can Automated Chip Synthesis be used with Physical Compiler?
Currently, Synopsys does not support the use of Physical Compiler
integrated with Automated Chip Synthesis. We are planning to make
this enhancement in the future.
2. How does acs_read_hdl compare to Presto?
The acs_read_hdl command uses Presto to analyze Verilog. In addition to
analyzing Verilog of specific files, the acs_read_hdl command is able to
search multiple directories to find all files required to analyze a
complete design, and it elaborates the complete design and leaves it in
memory.
3. In previous releases, if you had more than 10 libraries in your link
path, Design Compiler would crash. Is this still the same in the latest
release?
We are not aware of this problem. There are no new changes for this
release, in terms of handling libraries in your link path. If this
problem still exists, a possible workaround is to merge several
libraries into a single library.
4. Does Design Compiler keep the original hierarchy structure after
auto-ungrouping?
The original hierarchy structure is kept except for the blocks that
have been ungrouped by auto-ungrouping.
5. What are the differences between the two budgeters?
Design Compiler budgeter can budget RTL (elaborated .db) or mixed RTL
and gate logic in addition to pure gate logic. Design Compiler
budgeter also provides an added benefit of reduced file I/O because
you never need to exchange files (.db files, constraints) between
PrimeTime and Design Compiler.
There is an application note that provides more detailed information.
Please request this application note from your supporting AC.
6. How does budgeting handle high fanout nets to ensure no buffers will
be added during compile?
Budgeting propagates such attributes as dont_touch_network and
ideal_network the same way as characterize. Therefore as long as
your network is properly constrained at the top level so that
Design Compiler does not optimize it, the required attributes will be
passed down to the lower-level modules being budgeted.
7. Does ILM contain area and gate info?
Yes. For Design Compiler, the original netlist area is used for the
basis of wire load selection if area-based automatic wire load
selection is used. All interface cells, nets, pins, and logical
hierarchy are maintained.
8. In version 2002.05, is Presto enabled for VHDL?
No. It is planned in the U-release for beta.
9. Is the area information stored in the ILM .db file?
Yes; see question 7. Run report_area to see both the original netlist
and ILM area statistics that are stored in the ILM.
10. Are extracted timing models (ETMs) also context-independent?
No, ETMs are tied to a specific operation condition.
11. Do ILMs contain scan and test information?
Yes. The flow we recommend using is the test model flow (CTL - IEEE
Test Model standard), where scan and test information are supported
with ILMs.
12. Do ILMs contain power arcs information?
Only the information that is defined in the target library for the
library cells and macros.
13. Is the -physical option of extract_ilm available only in psyn_shell?
Yes.
14. Can you read a Design Compiler ILM into PrimeTime?
Yes, but the Design Compiler ILM does not support the use of
distributed parasitics (that is, DSPF, SPEF, and RSPF), whereas the
PrimeTime ILM does.
15. Do you have to remove_design before you read in your ILM?
Yes.
16. Can Design Compiler create extracted timing models (ETMs)?
No. ETMs can be generated only in PrimeTime.
17. If I have a STAMP model for an analog block, can I read that into
Design Compiler?
STAMP models can be used in Design Compiler.
18. Do ILMs have don't_touch attributes?
Yes, ILMs are marked as dont_touch and dont_touch_placement.
19. Would you lose loading information with -ignore_port?
Yes, which is why we will be coming out with an option to only pull
in all boundary loads for user-specified ports such as reset and
scan_enable. It is recommended to use -ignore_ports for reset and
scan_enable to avoid pulling in all registers in your original
design into the ILM.
20. Does Design Compiler include the transition of net n1? (slide 26,
side_load diagram)?
Yes.
21. Is U0 part of the interface logic (slide 26 in the tutorial) ?
Yes, it is part of the interface path from Reg1 -> U0 -> Out1
(Output Port).
22. Why would anyone want to exclude side_loads?
To create the smallest ILM model and speed up runtime; for example,
for a top-level optimization run.
23. Are ILMs going to be supported in the PSYN-Jet release?
Yes. They are supported in this release.
24. Can you read in Power Compiler generated ILMs into Design Compiler?
Yes, but without the physical information.
25. Are there any attributes that can be queried for ILMs?
You can check if a cell, net, or pin has the is_interface_logic
attribute.
26. How can Design Compiler balance the scan chain with the scan
inserted on the top- level with ILMs?
Each scan segment is kept in the test model that is part of the ILM.
27. Do ILMs contain scan information?
Yes. Scan information is in the test model that is part of ILM.
28. Does boundary optimization apply on ILMs?
No. All ILM cells are marked with a dont_touch attribute and cannot be
optimized in the current release. Optimization of ILMs (resizing /
buffering) will be addressed in a future release.
29. Can we remove the don't touch attribute on an ILM?
No.
30. Can we bring up an ILM in Design Analyzer or Design Vision?
Yes, just as you would with any structural netlist.
31. Does ILM work with reoptimize_design?
Remember that all ILM cells are marked with a dont_touch attribute, so
you cannot optimize an ILM with the current release (2001.08-PSYN-Jet).
32. Is there a way to force the RTL reader?
The -netlist option uses netlist reader only. The -rtl option uses
the Presto/HDL Compiler RTL reader.
33. Are you going to release the 64-bit VHDL reader?
No. It will be available with Presto-VHDL, which is planned in the
U-release for beta.
34. Now that Presto is the default, has the hierarchical defparam bug
fixed?
Presto supports defparam statements. You can change the value of a
parameter through a hierarchy of instantiations.
35. Is set_case_analysis new in version 2002.05?
No. Case analysis was introduced in the 2000.11 release.
36. Can you use multiple operating conditions in addition to multiple
trip points?
Operating condition consists of voltage, temperature, and process.
Among these three, on a working design at a particular time, voltage
can vary from block to block. Currently Design Compiler does not
support multivoltage.
Therefore, for single voltage support, there is no need for setting
multiple operating conditions. For min-max analysis, you might want
to use a different operating condition; Design Compiler can do that.
37. Since the default for trip points has been changed, will the delay
change as well?
It might change the delay with back-annotation information. But you
can reset the variables if you need to.
38. When the port has only one fanout, is port isolation still applied?
Yes. An input port can be isolated, regardless of its fanout.
However, if the port is already driving a buffer or an inverter, no
port isolation will be performed.
39. Would using set_isolate_port for the input port be the same as using
set max_fanout 1 on the port?
Regardless of its fanout, the set_isolate_ports command simply places a
buffer or inverter immediately AFTER an input port. The entire fanout
of the input port will then be driven by that buffer / inverter.
40. Do the Tcl enhancements include a warning (when using foreach) before
Design Compiler removes the collection from memory?
Not by default. There is a hidden variable, though, that you can set
in order to see a message whenever a collection gets deleted by using
foreach instead of the appropriate command foreach_in_collection. The
variable name is collection_debug_level; you have to set it to true.
41. Do the same improvements apply to non-Tcl commands?
No, the improvements are in the Tcl shell only.
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