( ESNUG 389 Item 4 ) --------------------------------------------- [03/06/02]
Subject: ( ESNUG 388 #18 ) VCS Rounding SDF Delays Doesn't Match PrimeTime!
> We've been annotating an SDF to a gate level netlist and seeing behaviour
> that doesn't link up with the results of our PrimeTime analysis. In
> particular, we're seeing scan chain shift issues caused by clock skew that
> seem to be okay in Primetime. It seems the skew that is seen between the
> flops in the VCS simulation is larger than that predicted in PrimeTime,
> slightly larger, and that's enough to kill our sims.
>
> My specific question is: how does one control the timing resolution in a
> VCS simulation that is annotated with an SDF? I've always assumed that
> the precision of the SDF would control the simulation precision. The SDF
> we have is specified down to 0.0001 nsec increments, but the simulation
> 'seems' to be running with a 0.01 nsec precision. It seems that we're
> hitting a situation where rounding going on.
>
> - Stephen O'Connor
> Cypress Semiconductor San Jose, CA
From: Brian Logsdon <brian.logsdon@philips.com>
Hi John,
Stephen really has an SDF with 100 fs resolution (0.0001 ns)? Ouch! That
gate sim is going to be slow. I'm glad it's him and not me running it. He
has described a common mistake... The SDF does not control the simulation
resolution. All the simulator does is annotate the delay information in the
SDF file into the timing arc variables of the gate models. Because the
simulator resolution is 10 psec, the simulator will either round off or
truncate the additional precision, depending on how the simulator was
written.
I was curious so I checked out the VCS manual and found the +delay_mode_unit
option to the VCS compiler. This is on page 3-21 of the Version 6.0.1,
"VCS/VCSi User Guide". I think this will solve his problem:
Set the 'timescale compiler directive to 1ns/100fs in the top level
source (probably the testbench) of the source files for the simulation,
including the testbench.
Then use the +delay_mode_unit option on the vcs command line. This will
force the compiler to use the smallest 'timescale it finds in the design.
Here is a potential problem: if you have a C-model or LMC model with fixed
timing resolution, and you are not running the simulator in the resolution
that the model wants, the model will likely not work. This is the case with
the LMC PCI models and it drives me bonkers!
- Brian Logsdon
Philips Semiconductors Tempe, AZ
---- ---- ---- ---- ---- ---- ----
From: Juan Carlos Diaz <juancarlos.diaz@massana.com>
Hi John,
Maybe I'm simplifying this, but it seems to me very similar to a problem
we had in the past with Modelsim. In fact, the solution was simulator
independent: no matter what the precision of the SDF file is, the
simulator will round the backannotated delays according to the "`timescale"
Verilog directive. Try to change the timescale to match your SDF accuracy,
and that's it, but remember there is a limit for this accuracy (consult any
manual to see this timescale limits).
- Juan Carlos Diaz
Massana Technologies Madrid, Spain
---- ---- ---- ---- ---- ---- ----
From: Stephen O'Connor <soconnor@silicon-packets.com>
Hi John,
Actually what Juan Carlos said is exactly what was going on. I discovered
that shortly after I mailed you John -- the `timescale in the library was
setting the precision. The root reason this was a problem SDF with lots of
tiny numbers for interconnect delays -- and I suspect these were the key
elements being rounded up.
My first suspicion was that VCS changing negative delays to zero which the
SDF also had was the issue, but gradually I figured it was precision issue.
And in retrospect it makes sense since the timescale directive is used at
compile time to set precision, and the SDF afterwards has to annotate those
delay elements, the directive would take precedence.
I also later got the detailed answer from the Synopsys VCS Support people.
The `timescale sets the precision, in our case our library had a 1ns/10ps
setup. Then if the SDF is a finer precision, which was our case, it gets
rounded off as follows:
0.001 -> 0.00
0.004 -> 0.00
0.005 -> 0.01
0.009 -> 0.01
Synopsys gives excellent VCS support.
- Stephen O'Connor
Cypress Semiconductor San Jose, CA
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