( ESNUG 388 Item 18 ) -------------------------------------------- [02/27/02]
From: "Stephen O'Connor" <soconnor@silicon-packets.com>
Subject: VCS Rounding Of SDF Delays Doesn't Match Our PrimeTime Analysis !
Hi John,
We've been annotating an SDF to a gate level netlist and seeing behaviour
that doesn't link up with the results of our PrimeTime analysis. In
particular, we're seeing scan chain shift issues caused by clock skew that
seem to be okay in Primetime. It seems the skew that is seen between the
flops in the VCS simulation is larger than that predicted in PrimeTime,
slightly larger, and that's enough to kill our sims.
My specific question is: how does one control the timing resolution in a
VCS simulation that is annotated with an SDF? I've always assumed that
the precision of the SDF would control the simulation precision. The SDF
we have is specified down to 0.0001 nsec increments, but the simulation
'seems' to be running with a 0.01 nsec precision. It seems that we're
hitting a situation where rounding going on.
I should point out that the SDF I'm using has CELL entries annotated with
IOPATH delays, and INTERCONNECT delays. The INTERCONNECT delays can be
smaller than the 0.01 value that VCS seems to be simulating.
Also the clock tree delays do not contain any negative delays, which could
be rounded to zero and aggravate the skew. Any help appreciated.
- Stephen O'Connor
Cypress Semiconductor San Jose, CA
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