( ESNUG 386 Item 15 ) -------------------------------------------- [01/16/02]
Subject: ( ESNUG 385 #6 ) Waaaay Too Many Hierarchy Tracing Tools/Techniques
> I am looking for a tool or script which will trace a specified reg or wire
> through the RTL hierarchy with possibly many name changes. When studying
> an RTL design which was writtem by somebody else, it helps to make drawings
> of one functional section of the design at a time. I find it very tedious
> to track nets through the entire RTL design. This process is especially
> difficult when there is a deep hierarchy with many name changes. Do you
> know of a tool which could solve this problem?
>
> - Chet Juall
> Dialogic
From: "Richard Hein" <richard_hein@agilent.com>
Hi John,
I've used a package called Renoir (now called HDL Designer I believe) from
Mentor Graphics. It has the ability to work out the hierarchy and draw the
block diagrams from the source files. Not sure if it now can display signals
through the hierarchy though. The primary use of the tool however is for
graphical HDL entry. I'm from the pre-HDL days when we entered designs using
schematic capture. When I moved to HDL I still had to draw block diagrams to
visualize the design. I've found the tool useful to visualize, design,
enter, manage and document a design so the next person won't have to trace
signals through the design and draw diagrams to figure out how it works in
the first place. I've only used it for FPGA design so I can't comment on how
suited it is to chip designs.
- Richard Hein
Agilent Technologies Ottawa, Ontario, Canada
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From: Jeffrey Ebert <ebert@sonicsinc.com>
John,
I highly recommend Novas Debussy to Chet. We have been using it for about 1
year now, I believe. Debussy supports tracing connectivity in the source
code window. It also will create a "pruned" schematic that only shows the
signals that you have selected. We use this feature RTL and gate-level.
- Jeff Ebert
Sonics, Inc.
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From: Howard Landman <howard.landman@vitesse.com>
Hi, John,
Avanti Formal (formerly Chrysalis, soon to be Synopsys) Design Verifier does
this automatically during the build process. You don't by default get a
report of every net, but when there's a difference found during verification
you'll see something like:
Different #1 - The two groups are different
+1 111134 A.pom1.bc_wdat[47]
-> NSB +1 64969 A.pom1.bc.$104641[7]
+1 111134 A.pom1.bc.bc_wdat[47]
+1 111134 A.pom1.fram.din[47]
PO +1 6928 A.pom1.fram.ram.DA[47]
+1 114461 B.pom1.'bc_wdat'[47]
-> NSB +1 78540 B.pom1.bc.bc_wdat[47]
+1 114496 B.pom1.fram.din[47]
+1 78540 B.pom1.bc.U5645.Z
+1 78540 B.pom1.bc.U6526.D1
PO +1 9154 B.pom1.fram.ram.DA[47]
In this case (an RTL-to-gates comparison) A is the RTL and B is the gates.
The cluster of names for A is all the different hierarchical names for that
logic signal in the RTL. Even inversions are included (with polarity -1
instead of +1) as variants of the same logic node.
In the gate level, notice that the library cell pin names on synthesized
gates are also included.
In both, the pins of excised submodules (in this case a data input "DA[47]"
to a RAM named "ram") will show up, but obviously the tool can't trace
through a module that it's been asked to cut out and throw away.
I think the necessary information to extract these clusters might exist in
the .hmap file produced by chrys_build, so it could just be a short Perl
script to get them from that. But I don't actually have such a script to
offer you. It is a text file:
% grep 111134 rtl_113001AB.hmap
S 111134 1 bc_wdat[47]
A 111134 1 0 bc_wdat[47]
A 111134 1 1 din[47]
but I'm not sure how to tell which node numbers are equivalent, and you'd
have to parse it all to get the hierarchy info surrounding those lines.
- Howard Landman
Vitesse Semiconductor Longmont, CO
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From: "Ray Salemi" <ray_salemi@mentorg.com>
Hi, John,
The Mentor tool HDL Detective will do this. Chet would be able to import his
design and view it graphically including tracking signals through block
diagrams. He can download it at http://www.hdldesigner.com
- Ray Salemi
Mentor Graphics
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From: Edward Arthur <eda@ultranet.com>
John,
This is what Debussy ( http://www.novassoft.com ) was invented to do. I'm
not affiliated with them, just a happy user.
- Ed Arthur
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From: "Adam Levinthal" <adam@gdsdomain.com>
Hi, John,
Novas Debussy is exactly what Chet is looking for. For textually oriented
users, it creates lists of module port connections for signals, and allow
the user to jump around the code looking at signal references. For visually
oriented users, it will create a schematic from the RTL and allow the user
to re-construct a logic fan-in or fan-out cone by clicking on ports in the
derived schematics.
I don't want this to sound like a sales pitch, but I would give up a lot of
other tools before giving up Debussy...
- Adam Levinthal
GeoLogic Design
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From: Richard Knight <rich@knighteda.com>
Hi John,
I have a tool called SUE that lets you travel up and down the hierarchy of a
design. Each time you step down/up, the port you came from is highlighted,
so it is very easy to know where you are in a design, and where you're
going. If you go to http://www.knighteda.com you will find a link to Micro
Magic tools. There's a description of SUE there.
- Richard Knight
Knight EDA Distribution
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From: Jeff Riley <jeff.riley@mindspeed.com>
Just thought I'd drop you a line and let you know that there is a GREAT tool
that does everything you ask and ALOT more. It's called Debussy and it's
from a company called Novas. http://www.novas.com Ever since I first used
this tool 2 years ago I have been completely addicted to it. Check it out.
- Jeff Riley
Mindspeed Technologies Boulder, CO
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From: Prab Varma <prab@veritable.com>
My company, Veritable Inc., has a design checking tool, Verity-Check, that
can perform hierarchical net tracing. http://www.veritable.com
- Prab Varma
Veritable, Inc.
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From: [ The Cat In The Hat ]
Keep me anon.
The Verilog to html converter, v2html, is a free Perl script that converts
Verilog designs into webpages. Once converted the webpages can be opened
directly in a browser. For more details, see:
http://www.burbleland.com/v2html/v2html.html
I haven't tried it yet, but a friend recommended it to me after some success
with it.
- [ The Cat In The Hat ]
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From: Duncan Crowther <duncanc@euro-eda.com>
Hi John,
I saw Chet's posting in ESNUG and thought I'd give you a pointer to a tool
that may help. Take a look at Expressive-III from Expressive Systems.
http://www.expressivesystems.com It's not exactly what you describe but
it does provide visibility of hierarchical signals throughout a complex
design. You would of course have to create your design hierarchy within
the tool first, but it's pretty fast to use. Anyway, I hope this helps.
- Duncan Crowther
EuroEDA Limited
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From: Gene Sullivan <gene.sullivan@analog.com>
My company has been using Debussy from Novas ( http://www.novas.com ) for a
couple of years now. The tool can trace through both RTL and gate netlists
(we use Verilog, by the way). For gates, the tool can draw schematics which
can be probed; nets can be expanded to show fan-in and/or fan-out cones.
For RTL, the tool draws reasonably good schematics and finite state machine
diagrams. The tool also has nice hooks into its waveform viewer. (This is
not a paid advertisement, I swear!)
I have heard that Undertow by Veritools offers similar capabilities, and it
may be cheaper. ( http://www.veritools-web.com/products.htm )
- Gene Sullivan
Analog Devices, Inc.
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From: Lee Bradshaw <bradshaw@ti.com>
Hi John,
The v2html tool may help Chet with navigating unfamiliar code:
http://www.burbleland.com/v2html
It seems to be more useful for finding the source of a signal than for
tracing fanout (especially across name changes.)
Your waveform viewer may have a logic browsing option to easily trace nets
through the hierarchy regardless of name changes.
- Lee Bradshaw
Texas Instruments
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