( ESNUG 386 Item 11 ) -------------------------------------------- [01/16/02]
From: "Rakesh Mehta" <rmehta2@nortelnetworks.com>
Subject: ASC's Vhdl2v Doesn't Convert VHDL Functions/Procedures To Verilog
Hello John,
I'm scrambling my head over this...
I am using VHDL-2-Verilog translator by ASC. I could not translate my
functions from VHDL to Verilog -- they are simply skipped!
My VHDL source code has a package which has some function declarations
(eg. calculate_lrc(data)) and definitions in it. The problem is when I try
to convert the package or code from VHDL to Verilog, the functions are
skipped. So the verilog file just has constants and no "function", as if
there was no function declaration in the original file.
I tried using -Function_Map option but it would only allow me to keep the
original function call but the parameters are skipped. Also no function
conversions.
So does ASC's vhdl2v not support function and procedure conversions from
VHDL to Verilog?
- Rakesh Mehta
Nortel Networks
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