( ESNUG 386 Item 3 ) --------------------------------------------- [01/16/02]
Subject: ( ESNUG 385 #4 ) You Can't Mix Avanti's Star-RC & Mentor's Calibre
> I need to generate a BACK-ANNOTATED RC extracted Spice netlist of a
> transistor-level design from a GDSII and a Spice netlist using Mentor's
> Calibre (for LVS) and Avanti's Star-RC. I would like to know if somebody
> has a methodology or script that accomplished this with these two
> different tools.
>
> - S. H. Park
> Api Networks
From: "John Lee" <john_lee@avanticorp.com>
Hi, John,
There is no known flow for this. Avanti and Mentor have been discussing the
possibility of this flow. I'm curious if other readers would be interested
in it; we are very willing to do this if customers request it. Star-RC (and
Star-RCXT) right now only reads LVS data from Hercules. To the best of my
knowledge, this, along with Calibre->xCalibre, are the 2 "real" commercial
solutions that do:
1.) Hierarchical LVS
2.) Have grey-box extraction capability from the LVS data-base
(hence are useful for full-chip).
I previously discussed in ESNUG 382 #6 some integration issues of fast-SPICE
simulators with RC extraction tools. Specifically, here are issues that I
think are most important:
a. Cost of extracting full-chips or full-blocks. This cost is usually
higher than need be, and here's why. During fast-SPICE simulation, it
is typical (for mixed-signal or digital blocks) that not all nets will
switch. That is, there is latency. In this case, not all nets need
to be extracted. This can save tremendously on runtime, disk usage,
and memory usage.
A good example of this is when designers want to verify the timing
performance of compiled SRAM's. The post-layout parasitics are *very*
important, and to acquire timing (setup/hold) of this from a fast-SPICE
tool (like any of the XXXX-Sim tools) involves simulating a very SMALL
portion of the nets in the SRAM.
How to do this safely, easily, automatically is an issue.
b. All new fast-SPICE simulators purport to be hierarchical. But how to
handle flat post-layout parasitics introduces problems with:
- capacity
- runtime
- back-annotation
Each tool on the market slows down w/ post-layout parasitics; how much
they slow down is dependent on the exact architecture.
c. How to easily call RC+fast-SPICE from a cell-based design flow (e.g.
for clock net verification, or critical timing path). It's a tough job,
and most companies, especially COT's end up not doing it.
Each fast-SPICE tool has strategies to do RC reduction, but the accuracy of
each approach varies...
- John Lee
Avanti Fremont, CA
|
|
