( ESNUG 385 Item 4 ) --------------------------------------------- [12/19/01]

From: "S. H. Park" <sh.park@api-networks.com>
Subject: How Do I Use Calibre And Star-RC For Transistor-Level Extractions?

John,

I need to generate a BACK-ANNOTATED RC extracted Spice netlist of a
transistor-level design from a GDSII and a Spice netlist using Mentor's
Calibre (for LVS) and Avanti's Star-RC.  I would like to know if somebody
has a methodology or script that accomplished this with these two
different tools. 

    - S. H. Park
      Api Networks


 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)