( ESNUG 383 Item 17 ) ------------------------------------------- [11/28/01]
Subject: ( ESNUG 382 #2 ) Rarely Noticed Library Characterization Gotchas
> None of the characterization software I've seen has handled the subtle
> tradeoff between setup, hold, and clk-to-Q delay in a way I would consider
> correct. Partly, this is a function of .lib format, which I feel is
> fundamentally broken in this regard. If you do a 3-D plot of setup, hold,
> and clk-to-Q for any given FF you will see that they trade off against each
> other in roughly hyperbolic fashion. Most systems characterize setup at
> infinite hold, and characterize hold at infinite setup, and then guardband
> them using some fudge factor. But it's possible for that process to arrive
> at setup and hold numbers such that, if you just barely meet the setup time
> and just barely meet the hold time, the FF doesn't work! Plus, as you
> approach the minimum setup or hold, the clk-to-Q delay increases. The .lib
> format has no mechanism for expressing any of these tradeoffs, even if you
> gather all the needed data. That forces the guardbanding to be
> unnecessarily large, which in turn reduces the accuracy of timing analysis
> and synthesis.
>
> - Howard Landman
> Vitesse Semiconductor Longmont, CO
From: Keith Howick <howick@siliconmetrics.com>
John,
I agree with Howard concerning proper modeling of the relationships between
setup, hold and delay. It's odd that this remark comes now as I'm presenting a
paper on this subject at DesignCon 2002. Understanding these relationships is
very important since most dynamic glitches (mentioned originally by Mr. Kalita
from Intel) are a result of improperly constraining the sequential device.
I also agree with Howard that, regardless our understanding of the physics,
all characterization tools are limited in their efforts by the models they
must build. None of the model formats popularly supported today for static
timing analysis can fully represent the setup-hold-delay relationships. At
the very least, a model would require a table of hold vs. setup and the
setup slew, and a table of delay vs. both setup and hold.
We solved the problem to the best degree today's models will allow with two
measurement features: delay degradation and dependent setup and hold. We
discovered that many of the timing difficulties our customers encounter
disappear when these two measurement styles are applied.
Measuring setup and hold using delay degradation gives the library developer
the ability to trade off the predictability of the model with the cell
performance the model represents. Howard's correct that clock-to-Q prop
delay increases as setup or hold approach the cell's breakdown condition.
Since this isn't reflected in STA models it behooves the library developer
to avoid it. But by how much? Without having some measurable cell behavior
the developer is just guessing, adding a fudge factor. Using the degradation
of delay as a reference the user can control how much modeled performance is
given up to preserve model predictability.
Measuring setup and hold in a dependent manner, as they should be, further
avoids dynamic glitches. While assisting a customer with a modeling problem
we rediscovered an age-old truth: setup and hold are not independent
measurements. The combination of setup and hold results in the minimum
pulse-width of a synchronous pin (e.g. data). The two measurements are
needed to accomodate the dependence of synchronous MPW on its relative
location to the clock. Unfortunately, today's models only allow one of the
two dimensions of these constraints to be represented; either the dynamic
pulse width is represented and the relative location lost, or the relative
location is preserved but the dynamic pulse width is lost. Fortunately,
correctly characterizing setup and hold in a dependent fashion avoids many
of the timing difficulties this modeling weakness permits.
Thankfully, using both these methods avoids dynamic glitches due to pass
gates. Doing so also reduces the number of vectors applied to a SPICE
netlist for verification. Since most sequential designs don't have limits
for maximum transition time or minimum frequency designers need only test
their cells at the values of setup and hold reported by characterization;
reducing the vector set to the 2^(2*n) vector set reported by Howard.
- Keith Howick
Silicon Metrics Corp.
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