( ESNUG 381 Item 6 ) -------------------------------------------- [11/08/01]
From: "Dhrubajyoti Kalita" <dhrubajyoti.kalita@intel.com>
Subject: Tuxedo LTX With Verplex LEC Failed To Find Our Dynamic Gliches
Dear John,
We are trying to verify our standard cells by ensuring that vendor provided
Verilog models are equivalent to the SPICE netlist. Using Tuxedo LTX, we
tried extracting a Verilog model from the SPICE netlist and then verifing
equivalency between the extracted Verilog model and golden Verilog model
by running Verplex LEC.
This flow failed to detect a previously known dynamic glitch caused by a
pass transisitor in one of the standard flops. It appears that the only way
to detect this kind of glitch is through SPICE simulation.
I would like to know if there's an automated way to generate exhaustive
input stimulus to verify functionality of sequential cells. For
combinational cells, this can be easily automated, but I could not find
an automated way to generate test input for sequential cells. Any user
input will be highly appreciated.
- Dhruba Kalita
Intel
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