( ESNUG 380 Item 5 ) -------------------------------------------- [10/25/01]
From: Don Dattani <dond@zucotto.com>
Subject: I'm Not Getting Quite The Scan Vectors I Wanted From TetraMax
Hi, John,
My question pertains to generating test patterns with TetraMax that can be
used in a gate level simulation. My design heirarchy consists of:
- a core (full-scan chain with MUXed flip-flops)
- a TAP controller and scan logic
- a bunch of other I/O
With TetraMax, I used
create_test_patterns -output core.vdb
write_test -input core.vdb -output corepatterns.v -format verilog -first
1
This generated a huge test that applies patterns at the core inputs, toggles
clocks, and checks outputs. What I want to be able to do is tell the tool
that I have a scan chain in the core so that the ATPG generated patterns
will be applicable to *BOTH*:
1) the core inputs (as applied at primary inputs)
- and -
2) the scan chain.
In simulation I imagined that this pattern would be loaded with the TAP,
then I'd toggle the clocks, scan out the patterns and validate the scan
chain and the primary outputs.
How do I get TetraMax to generate such a pattern?
- Don Dattani
Zucotto Wireless, Inc. Ottawa, Ontario, Canada
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