( ESNUG 380 Item 4 ) -------------------------------------------- [10/25/01]
From: [ Mr. Bigglesworth ]
Subject: Verplex (Again) Tramples Chrysalis & Formality In User Benchmarks
Hi John.
I thought I would share this data with you. Keep me anonymous on this.
We've been looking into a formal verification solution that can handle our
big chips. From a technical standpoint, it seems like a no-brainer.
Chip 1 (RTL2Gate) 2.5 M gates, hier design:
Time Memory
-------- ---------
Avanti Chrysalis 3.0 527 min 1310 Mbyte
SNPS Formality 2000.11 No Data* No Data*
Verplex Tuxedo 2.0.8.a 6 min 302 Mbyte
* - Formality had setup problems
Chip 2 (Gate2Gate) 4 M gates, flat design:
Time Memory
-------- ---------
Avanti Chrysalis 3.0 3596 min 14870 Mbyte
SNPS Formality 2000.11 112 min 2399 Mbyte
Verplex Tuxedo 2.0.8.a 89 min 2817 Mbyte
Chip 3 (RTL2Gate) 7.5 M gates, hier design:
Time Memory
-------- ---------
Avanti Chrysalis 3.0 255 min 1300 Mbyte
SNPS Formality 2000.11 No Data* No Data*
Verplex Tuxedo 2.0.8.a 34 min 697 Mbyte
* - Formality had setup problems
Chyrsalis Design Verifyer was the most complicated to run. Formality
was also difficult to setup, but not as bad. For Tuxedo, within 30
minutes, we had everything up and running and comparing.
- [ Mr. Bigglesworth ]
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