( ESNUG 380 Item 1 ) -------------------------------------------- [10/25/01]
From: [ Captin Krunch ]
Subject: Real Life Experiences w/ MoSys, Virage, & Artisan Memory Compilers
Hi John -
I noticed your DAC report was light in the IP memories area. Keep me anon
please, but here's some real-life information to fill people in:
1) The MoSys RAMs look like a good idea, and the people supporting them
are nice (though there aren't very many of them). However, they are
generally device people, not logic designers. Also -
a) The MoSys test suite works only if you can bring all the pins of the
RAM to the pins of your chip (and their nominal form factor is x128).
Otherwise you have to develop your own test patterns and methods of
telling the fuse burner what to do.
b) MoSys hasn't addressed the soft-error issue, so make sure you leave
plenty of room for (non-MoSys) RAMs for parity and ECC (especially
if your application is byte-wide). (It's a shame MoSys didn't
adjust their form-factors for this).
c) Fuses add to your processing and testing costs (and don't help with
soft-errors).
2) The Artisan memory compilers are pretty good. However, when Virage beat
Artisan to market for 0.15u last year, our company switched to Virage.
(Virage claimed better performance as well). Big Mistake! Virage
apparently bought its compiler technology at K-mart. Very immature
physicals, lots of bugs and problems. Artisan's compilers are much more
solid and mature. (And if Artisan and Virage are listening - can't you
guys agree on a common naming/byte-masking convention for your ports?)
I would love to hear what others have seen with Artisan, Virage, and MoSys.
- [ Captin Krunch ]
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