( ESNUG 379 Item 14 ) ------------------------------------------- [10/11/01]
From: Siegfried Weidelich <Siegfried.Weidelich@McDATA.com>
Subject: What Are The Pro's And Con's Of Sync vs. Async Resets In Designs?
Hello, John,
We currently use synchronous resets in our ASIC designs. We are finding a
lot of time is spent meeting timing on synchronous resets, especially at
clock speeds 200+ MHz. We are considering switching to asynchronous resets
so that the logic connected to the D pin is not impacted by reset.
Can someone list the pros and cons of sync vs. async resets? Are there RTL
versus gate simulation issues? What are the PrimeTime and test issues?
How do you avoid them?
- Siegfried Weidelich
McDATA Corporation
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