( ESNUG 379 Item 10 ) ------------------------------------------- [10/11/01]
Subject: ( ESNUG 377 #22 ) SmartModels Are Faster In NC-Verilog vs. NC-VHDL
> Has anyone else experienced relatively poor performance of SmartModels on
> NC-SIM when compared to the MTI simulator? Is there some inherent
> difference between the two simulators that would explain the difference
> is simulation times? Is the NC-SIM poor performance limited solely to
> VHDL simulations or does it include both VHDL and Verilog simulations?
>
> - Paul Stuverud
> Unisys Corp.
From: "Mick Posner" <mposner@synopsys.com>
Hi John,
I can shed some light on Paul's issue but I am afraid that I cannot solve
the problem he has. First of all some clarification. If the model is of
a vendors proprietary ASIC, then it would have been created by either the
Synopsys Verilog Model Compiler, VMC, VHDL Model Compiler, VhMC or the
C Model Compiler, CMC. The vendor uses the compiler to create a model
that interfaces with the simulator via the SWIFT interface. The models
look a lot like the Synopsys SmartModels but the vendor supports the model
function, Synopsys only supports the models creation. We call these SWIFT-
based models, not SmartModels. SmartModels are the Synopsys created and
supported verification models shipped and licensed as part of the DesignWare
library.
I expect the reason Paul is seeing different simulation speeds between
MTI and NC-SIM is down to the way that each simulator interfaces to SWIFT.
This is, of course, a guess as Synopsys does not have access to MTI or
NC-SIM.
MTI created their own direct interface to SWIFT. They have a layer in their
simulator kernel that talks directly to the SWIFT model thus their is
minimal interaction overhead. Synopsys VCS and Scirocco interface to SWIFT
in the same way & have the added advantage of interfacing via a full bussed
model interface. This yields even more simulator model performance.
NC-SIM has two interfaces to SWIFT. If you access the SWIFT based model on
the VHDL side you are going through what I think is the same SWIFT interface
that was used in Leapfrog. If you access the SWIFT based model via the
Verilog side you have a slightly different interface. On the Verilog side,
you make use of what is called lmtv, Logic modeling to Verilog. This is the
Synopsys written and supported SWIFT interface for NC-Verilog. I expect
the Synopsys lmtv interface is more optimized that the old Leapfrog one.
Feel free to pass on my name to Cadence. I would be happy to work with them
to improve the performance of their SWIFT interface. A slow SWIFT interface
does not look good for both Cadence and Synopsys.
- Mick Posner
Synopsys Beaverton, OR
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From: "Paul Stuverud" <Paul.Stuverud@Unisys.Com>
Hi, John,
Since I posted this message, we have identified the root-cause of the
problem and implemented a solution. Here's a summary of what we found:
Cadence revealed that there are actually two different PLI's developed...
one for NC-VHDL, and another for NC-Verilog. The PLI for NC-Verilog was
actually written by Synopsys. The PLI for NC-VHDL is a derivative of an
old Leapfrog interface that has been migrated forward. Because of this,
there is more efficiency when running Synopsys SmartModels in NC-Verilog
vs. in NC-VHDL.
So what we're doing is running mixed-mode simulation. The SmartModel is
running in NC-Verilog, and the rest of our circuit is running in NC-VHDL.
The performance is now acceptable.
By the way, it's too bad I didn't post this problem on ESNUG months ago.
We originally ran into it back in late June and didn't didn't ID the root
cause until early Sept! We didn't think to compare NC-Verilog and NC-VHDL
runs until very late, even though we had both versions of the model and
simulators avail to us early-on.
- Paul Stuverud
Unisys Corp.
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