( ESNUG 376 Item 2 ) -------------------------------------------- [08/29/01]

Subject: ( DAC 01 #8 ) C-Level Says 'Thanks'; SystemC Cries 'Missing Data'

> The second embarrassment for Synopsys here is, after all this grief,
> C-Level's "System Compiler" is beating the crap out of Synopsys's
> "SystemC Compiler"!!  Three months ago at SNUG'01, Dan Joyce of Compaq
> reported the first C-Level tape-out.  Below, I have 6 more designers
> reporting either that they're using C-Level "System Compiler" for current
> designs or that they've already taped out with C-Level.  In contrast,
> there's only 1 guy around talking about using Synopsys "SystemC Compiler"
> for a design *plus* a lot of other user letters saying how they tried
> but couldn't get SystemC to work!  Ouch!


From: Dan Skilken <dans@cleveldesign.com>

John,

Thank you very much for all your support, and the DAC report.  I am glad
my users responded, and I truly appreciate your coverage.

In a way, I see C Level playing in a different area than SystemC and 
Cynapps.  I don't know how many people realize it.  We are just 
supporting synthesis from the way people have been using C/C++ to 
model hardware for years.  It is a cycle accurate approach that 
delivers the kind of simulation performance that engineers expect out 
of using C.  We have just added some things like a synthesizer, style 
checker, and other widgets to make the simulations easier or more 
accurate and to connect the methodology to the rest of their design 
flow.

The nice part - simulation execution becomes free.  The added value is the
performance is 300 X the fastest HDL simulator.  For this kind of
performance, and at that price, customers do look at this method
differently than any other "C based" solution.  We have made a lot of 
enhancements to support a broader range of designs.  This methodology has
sold to a who's-who list of successful electronics companies (up to about
30 by now.)  All are using it on mainstream designs and major projects.  If
we weren't in mainstream companies and projects by now, I would start to
doubt whether we had a real market.  (Now that I'm a CEO I have to start
worrying about these sorts of  things....)

I see us filling a gap in the current system  verification area that HDL
performance is giving customers problems right now.  (Ultra large designs
mean ultra large simulation data.)  We don't replace HDL -- we can't and
don't want to -- that's how we make money, by connecting this C/C++
verification technique to HDL design.  Perhaps our efforts here will change
how the industry charges for simulation.

Shouldn't the simulation execution be free, and the value in debugging,
and simulation interface be where the EDA vendors add value?

    - Dan Skilken, CEO
      C Level Design, Inc.                       Campbell, CA

        ----    ----    ----    ----    ----    ----   ----

From: Kevin Kranen <kkranen@synopsys.com>

Dear John,

Congrats on getting out your truly massive DAC report, but I'm pleased, as
an EDA marketing guy, to be able to chastise you for two shortcomings:

  1) Your report almost entirely misses a $100 Million segment of the EDA
     market - system design tools or ESL as Dataquest/Gartner calls it.
     Your report fails to mention either the segment or any of the
     market-leading tools in this space, including Synopsys CoCentric System
     Studio/COSSAP, Cadence SPW/VCC, each of which bring in more revenue
     (each north of $20M/yr if you look at DQ estimates) than most of the
     startups in your report.  You also missed a number of other smaller
     folks such as Virtio, TILAB, Dynalith, and only had unconnected dribs
     and drabs on other such as CoWare N2C, Frontier Design, Tops, Vast,
     CARDtools Systems, Hyperformix(SES), Y Explorations, AXYS, etc.  Where
     is this missing "matter" in the DAC ESNUG universe?

  2) You missed some obvious CoCentric SystemC Compiler tapeouts from March
     of this year at EuroSNUG, one from Siemens and one from Fraunhofer that
     won BEST EuroSNUG PAPER.  You've also missed a number of chips that
     were designed at the architecture level in SystemC, refined, then
     implemented in traditional HDL methodology such as the two projects
     done by Infineon highlighted way back in Jan. of 2000 !! 

Sincerely,

    - Kevin Kranen, SystemC Marketing
      Synopsys, Inc.                             Mountain View, CA


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