( ESNUG 371 Item 1 ) -------------------------------------------- [05/23/01]
Subject: ( ESNUG 370 #6 ) PhysOpt's Placement Of Clock Gating Cells
> I'm a PhysOpt AC in Dallas. I can't answer Neel's question about Power
> Compiler, but I do know about using PhysOpt with Cadence and Avanti CTS
> tools. ... My specific flow steps may need to be tuned for each customer's
> environment, but it's a good starting point...
>
> - [ A Dallas PhysOpt AE ]
From: Neel Das <neel.das@corrent.com>
Hello John,
I have some preliminary data to report on PhysOpt and clock gating cells.
We're not using integrated clock gating cells, which makes this case *very*
interesting for us.
Around 71% of the clock gates have less than 10 um between the main gate
and the enable latch. Here's how PhysOpt placed them:
< 10 um - #################################################### 105
10 to 20 um - ################ 32
20 to 30 um - #### 8
30 to 40 um - # 2
> 40 um - 0
Total clockgates 147
I can provide more info later if you'd be interested... I'm curious to see
how our router handles these.
- Neel Das
Corrent Corporation
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