( ESNUG 368 Item 13 ) -------------------------------------------- [04/12/01]
From: "Sean W. Smith" <sesmith@cisco.com>
Subject: Sean's Trip Report from 2nd Annual Verisity Users Group Conference
Hi, John,
I thought I would share my impressions of the recent 2nd annual Verisity
users group conference. Overall there were a quite a few more attendees than
last year. Surprisingly still not a large turnout from the specman
veterans. Overall the conference was a significant improvement over the
first year. The steering committee did an excellent job of taking the
feedback from the first event and tailoring the event more toward what
people wanted. One thing that I wanted as well as most other attendees was
more technical user presentations as well presentations by Verisity R&D and
field staff on application of specman. Those who attended were rewarded
with a number of highly technical presentations by users, Verisity, and
Verisity partners such as Qualis design. The event ran on time with a
friendly atmosphere and the food was very good. This conference is
certainly not DAC for extravagance but if you're a verification engineer and
work with specman at all you would be well served to attend. There was
enough variety in the presentations to please novices and specman guru's.
Below is a brief synopsis of the presentations I attended.
Tutorial: Advanced Random Data Generation - Pete James, Qualis Design.
~3 Hours. Pete went through three sections from 1 of Qualis' specman
training classes. 1st section was a verification strategy overview covering
strategy, test plan, metrics, coverage, etc. The other 2 sections covered
generation techniques used in an ATM environment including transaction and
scenario verification. Presentation was excellent the code examples were
complete and well thought out.
Tutorial: Writing eVC's - Sholmi Uziel ~ 90 minutes.
This was a great overview on some coding style guidelines and methodologies
for writing an e verification component (aka re-usable model). This
presentation was a great addition to the presentation Janick Bergeron made
last year. I found it a good reference to Verisity's current preferred
methodology. Presenter did a great job and was able to easily address
questions.
Tutorial: Writing efficient 'e' code - Verisity R&D ~ 120 minutes.
This presentation was a favorite of myself and other specman power users.
One user comment that this presentation made the whole trip worthwhile.
I agree. Verisity dives in detail into profiling 'e' code. Verisity now
has profiling tools for runtime, memory and temporal expressions. Some
very interesting examples were shown and the actual implementation was
discussed to give advanced specman users a better chance of writing
efficient code. I hope this topic is covered again next year and in an
advanced training option. A+
The Evolution of Verification methodology: From Directed Tests to Specman
Elite: Mark Strickland, Verisity.
A basic introduction into the evolution of verification and where specman
fits in. This presentation was primarily targeted and novice or non-
specman users.
Randomized Testing with a Reference Model Based Testbench: Greg Mokler, TI
A very good presentation on dealing with real world problems and how Greg
and team were able to use a c reference model in conjunction with specman
to solve a verification problem. Also provided a nice example of closing
the verification feedback loop by writing coverage metrics against a FSM
and then using the specman coverage API to steer random generation into
the uncovered areas. An example of this type of technique can be found
in the Verification Advisor included with specman elite.
Coverage Metrics, Understanding Functional and Code Coverage: Mark Savoldi
and Sean Smith, Cisco Systems
A practical overview of code coverage, functional coverage, pros and
cons of each technique and suggestions for a hybrid approach to give
users objective feedback on verification completeness. I think Mark
did an excellent job of presenting this very misunderstood topic.
Keynote Address: Knowledge Transfer: Yoav Hollander, Verisity.
Yoav's ramblings are always one of my favorite topics. Despite running
on empty after a long and delayed international journey, he still managed
to give a thought provoking, entertaining but concise speech on where he
thinks knowledge transfer is headed and why it is so important. Yoav's
slides would not translate well without his presentation and humor. Those
who have not attended previously or ever met Yoav are missing out. A 5-10
minute of discussion with the father 'e' can be very enlightening. The man
is a walking encyclopedia of verification knowledge and so willing to
share what he knows...
An Eight Step Approach to Experience Random Verification - Chirs Macionski,
Qualis Design.
Great overview for beginning specman users on how to define a good directed
random test methodology. The steps and presentation were clear but
personally I found the code examples were poor and definitely needed
improvement. This appeared to be a very popular presentation amongst the
attendees for teaching some basic techniques that can be used in specman.
Aspect Oriented Programming - Amos Noy, Verisity.
A theoretical and abstract discussion of OO lanuages and there limitations
in the hardware verification spec. Introduces the concept of aspect
oriented programming and talks about some unique features 'e' possesses
relative to other OO languages and how this benefits verification
engineers. Some talk about the future of 'e'. This was one of my favorite
presentations but this presentation was the most abstract of all and
certainly seemed to confuse or have little value to many attendees. I hope
they continue to offer topics such as this in the future.
Implementing a temporal coverage model - Craig Deaton, TI
This presentation was another real world problem/solution scenario. Craig
basically went through a methodology for testing a complex arbiter. The
presentation may have been confusing for those not familiar with temporal
expressions but I enjoyed it and it triggered some good ideas that I want
to apply to my current effort. Not necessarily, a beginners presentation
but worthwhile and certainly the type I enjoy.
Verifying a CPU Core - Jon Rijk, ARM - Two part presentation.
First part was about transaction scoreboarding and gave a reasonable
introduction to the concept. The 2nd part of the presentation talked
about random CPU instruction and program generation. Well Presented...
Verification Vault - Ric Chope, Verisity
Ric presented a brief overview on Verisity's new online support site
and user community. This new offering will be of great value to specman
users. I'm looking forward to the public launch.
Emulating an RTOS - Eric Owens, Verisity
Eric presented some interesting concepts for emulating an RTOS in 'e'.
This presentation seemed to have mixed reaction. I personally enjoyed it
and thought it documented some techniques I had been unknowingly
using and gave me some good enhancement ideas for my application. Some
others I spoke with seemed perplexed as to why you would even want to
do this? The code examples I thought were very good and I plan on using
this technique when applicable.
e to Verilog: Brian Van Essen, Cisco Systems
Brian presented an overview of the 'e' 2 verilog research project. Cisco
has been partnering with the University of Tubingen, Germany to develop
a "proof of concept" 'e' synthesis tool to explore the possibilities of
using 'e' as a hardware/system design language. For more information see
"A framework for Object Oriented Hardware specification, Verification
and Synthesis" in the proceedings of DAC 2001.
R&D Panel: Various folks from Verisity fielding questions from the audience.
Pros with this format was that everyone got hear the questions & answers.
Cons: This Structure (versus the R&D Round table last year) limited the
conversational nature of the some of the questions, and verity marketing
answered too many questions. I hope in the future Verisity marketing
takes a less active role in censoring content at the conference.
I apologized as I missed the STARC presentation, knowledge transfer panel,
and the Verisity update stuck in traffic trying to drive to Lake Tahoe as
half of the bay area appeared to be doing that Friday afternoon.
In Summary a very good experience for specman users: Pros: Free, good food,
good mix of technical material from beginning to advanced, good networking
opportunities, opportunities to have one on one conversations with Verisity
developers. Cons: My brain hurt from information overload by the end, a
little too much marketing, need even more user presenters. I conclude with
a couple of quotes from the conference, comments and feedback are welcome.
I apologize if I omitted anyone or their presentation....
QUOTES:
"There is a group of hunter gathers traveling up & down the east cost
spreading the knowledge of fire, stone tools and socket based
verification" - Yoav Hollander
QUESTION to one of the presenters: "Why did your company switch from
Vera to Specman?" ANSWER: Long Pause "because Vera sucks!" longer
explanation then followed. - Anonymous Engineer
BEST ANALOGY: Peet James and Chris Macionski - quoted from their paper
Shotgun E
"An analogy to this approach is to fire a shotgun at a target -- a large
percent of the verification space is covered with a few strategic shots
(or testbases). After looking at the target (or coverage reports), you
would target specific uncovered areas with a high powered sniper rifle
(directed testcases). The old-school, directed verification strategy
using HDL is like a using a pea shooter to individually target the gnats
(bugs) within the verification target area. The new-school way, if done
correctly, will need only a few sniper shots near the end of the
verification project"
Happy Bug Hunting,
- Sean W. Smith
Cisco Systems RTP, NC
( ESNUG 368 Networking Section ) --------------------------------- [04/12/01]
Concord, MA -- AVAYA Networking seeks ASIC architect, design and
verification talent. No headhunters, please. "shopkinson@avayactc.com"
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