( ESNUG 368 Item 12 ) -------------------------------------------- [04/12/01]
From Neel Das <neel.das@corrent.com>
Subject: What's The Real Dirt On PhysOpt With Power Compiler & CTS Tools?
Hi, John,
I applaud your continuing efforts with ESNUG.
I would be very interested to get feedback on how good the hooks are between
Power Compiler and Physical Compiler in the following two instances
(particularly for designs well over 100MHz):
1. With integrated clock gating cells being available
2. Without integrated clock gating cells being available. In this case,
Synopsys claims localized grouping within PhysOpt will ensure the
clock gating elements would stay together in layout. Has anyone had
any experience with this in a *real* tapeout flow? Has the CTS tools
you used with PhysOpt / Power Compiler handled skew management well?
Additionally, how's the interaction if the clock gating cells have
observability/controllability ports?
- Neel Das
Corrent Corporation
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