( ESNUG 362 Item 7 ) --------------------------------------------- [11/30/00]
Subject: ( ESNUG 359 #7 ) My Design's Small; I Need Cheap-But-Good ATPG
> Do any of your many well educated and knowledgeable readers have some
> cheaper ATPG tools to recommend? I won't be generating scan for a million
> gate ASIC so a small tool would work nicely. We can't afford the Mentor,
> Cadence, or Synopsys products, and our design is small. Right now I'm
> working on a very small, specialized design that's only 7 kgates. I don't
> need to buy a $300K suite of tools for this. Ideas?
>
> - Morgan Monks
> Gain Technology Phoenix, AZ
From: Ira Hart <ihart@galtdesign.com>
John,
For a larger design, scan is a must. You may find that for a small 7K gate
design, it would be more worthwhile to write test vectors by hand.
You probably will have a suite of verification tests you can use for a
start. Your ASIC vendor will give you fault grade results to let you know
where the holes are. You can fill in the blanks to get reasonable coverage.
If you are doing a 7K gate design, you are probably doing a cost sensitive
high volume product as well. You will find that adding scan to a design
will increase your sequential gate count by around 40%. This will cost you
$$$ if you get bumped to a larger die size due to the addition of scan.
- Ira Hart
Galt Design Inc. Newton, MA
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From: [ I Wear My Sunglasses At Night ]
Hi John,
Keep me anonymous please. Morgan should check out AMI. They have their
own tool that can insert scan and do ATPG. His size of design is also in
their sweet spot, if he doesn't need blazingly fast technology.
If he has a design with reasonable volume, he should be able to get the
scan insertion and ATPG thrown in.
I used to work there and I inserted scan on a lot of designs, and got
fault coverage >90% almost all the time, and >95% with a little work on
designs where this was required.
I don't think they sell the tools, or contract out the service, but it
might be worth asking the question.
- [ I Wear My Sunglasses At Night ]
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From: Veli-Matti Karppinen <veli-matti.karppinen@pigroup.fi>
Hi John,
A possible tool could be the old Attest/Zycad/TSSI/ and now Fluence TDX-ATG.
At least it used to be cheaper than ones Morgan mentioned and in my
experience does the work OK.
- Veli-Matti Karppinen
PI-Group Somewhere, Finland
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From: Ken Butler <kenb@ti.com>
John,
I noticed Morgan Monks' post about cheap-but-good ATPG. I don't have a web
site to tell him to look, but there are a number of universities over the
years that have developed ATPG tools that they will give out freely.
Probably the one that shows up the most frequently in research papers is
HITEC from the University of Illinois.
HITEC formed the basis for what became the Sunrise tools, portions of which
are as we speak being ported into Synopsys TetraMAX. HITEC's claim to fame
was sequential ATPG, which may or may not be what he wants.
I believe that Dong Ha at Virginia Tech (?) had another tool called, I
believe, ATLANTA. That might be worth a look.
The problem with most tools like these might possibly be an inability to
read whatever netlist format he's using and/or not being able to handle
complex design structures like tristate buses or other non-FF and non-
combinational gate type stuff. Nothing ventured, nothing gained I guess.
- Ken Butler
Texas Instruments Dallas, TX
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From: Mike Kondrat <mikek@fluence.com>
Hi John,
In your ESNUG 359, Morgan Monks asked about low cost ATPG tools. I know I
am a marketing weenie but I wanted to let your reader know that our ATPG
tools are low cost compared to the big boys. His application would be a
good fit for our TDX product.
- Mike Kondrat
Fluence Technology Beaverton, OR
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