( ESNUG 359 Item 5 ) --------------------------------------------- [9/13/00]
From: Subha Pindiproli <Subha.Pindiproli@emulex.com>
Subject: Designer Seeks DC/PT Script To Detect Paths Across 2 Clock Domains
John,
I have a world with two clock domains:
SysCLK Domain PCI CLK Domain
------
| |
-->| ff |-------->|----------|
| ------ | |
| | comb. | Sync FF's
| ------ | logic | ------ ------
| | ff | | | | | | |
|-->| |-------->| |------->| |--->| |----> FSM
| ------ | | | | | |
| | | ------ ------
| ------ | | |__________|________ PCI_CLK
| | ff |-------->|__________|
|-->| |
| ------
|
SYSCLK
As you can see from the above diagram, the output of SYSCLK FFs go into some
combinational logic and feed into FFs clocked by PCI_CK. The outputs of
the PCI_CLK FFs go into a FSM.
Let's say a glitch were to occur at the posedge of SYSCLK:
1) This could trigger a false (high) start signal and the output of
combinational logic would register a high. Because PCI_CLK has no
way to verify that this is a glitch, not a valid signal, it would
start the PCI_CLK FSM.
2) The correct solution is to put another FF after the combinational logic
clocked to the SYSCK, thereby preventing this glitch.
Are there any DRC tools out there that might catch this type of problem? Do
your users have any DC scripts that could test for this type of problem?
- Subha K. Pindiproli
Emulex Network Systems Costa Mesa, CA
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