( ESNUG 357 Item 4 ) --------------------------------------------- [8/10/00]
Subject: ( ESNUG 356 #0 ) "Hot" Tech Docs & Users Debugging Beta "Presto"
> I recently became aware of an apparently undocumented variable in ver
> 2000.05 of Design Compiler: hdlin_enable_presto
>
> Synopsys informed me that setting this true will help the HDL Compiler
> "work better" but I haven't had a chance to test this out (yet). I was
> curious if anyone else had heard of this variable or had any feedback on
> it. Thanks.
>
> - Jeff Waite
> Netergy Networks, Inc.
From: Peter Kamphuis <peter.kamphuis@infineon.com>
Hi John,
The hidden variable "hdlin_enable_presto" is not so hidden at all.
Recently I attended Synopsys' Synthesis 2000 Seminar, presenting new and
changed features of the 2000.05 software. One of the slides showed:
New HDL Compiler - Presto
* Re-architected HDL Compiler for Verilog
(VHDL support in an upcoming release) [2000.11 ?]
* Over 50 verilog customer designs tested,
- 6x average runtime improvement over 1999.10
- 35% less memory than 1999.10 release
* Set the following dc_shell variable to enable
the New HDL Compiler
dc_shell> hdlin_enable_presto = true
dc_shell-t> set hdlin_enable_presto true
BTW, even the 2000.05 HDL Compiler Release Notes describe this variable.
As far as I can remember I was told that it's a completely new piece of
software. And as with all new software, there might be bugs in it.
That's probably why it's not yet used as default.
- Peter Kamphuis
Infineon Technologies AG Munich, Germany
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From: [ A Little Leprechaun ]
John,
Attached, you should find some preliminary info from Synopsys on Presto.
I'm not be allowed to distribute this outside our company, so don't tell
anyone where you got it from, and keep me anonymous.
- [ A Little Leprechaun ]
Editor's Note: What Leprechaun sent me was a 51 page PDF Synopsys tech
doc that completely outlines what Presto is, how it works, its switches,
everything. You can download your own copy of what he sent me at
http://www.DeepChip.com (look in the new "Downloads" section.) It's
interesting reading. (And I wonder how long it'll be before I get
another nastygram from Synopsys Legal for publishing it...)
- John Cooley
the ESNUG guy
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From: Clint Olsen <olsenc@ichips.intel.com>
John,
That hdlin_enable_presto was covered in Synopsys' most recent tutorials
covering DC 2000.05. It's not undocumented since I was able to file a STAR
against it. The switch enables Synopsys' "new" Verilog reader (Presto HDLC)
and supposedly handles some Verilog "corner cases" more robustly. For
example, don't-cares in expressions are supposed to be better handled (the
current Verilog reader is busted IMO) and the overall memory footprint of DC
when doing a "read -f verilog" is purported to be much less.
However, I managed to find a bug in the damn thing after a few minutes of
use with the "~" operator (requires parenthesis around it's arguments.
Oops). It is in "extended beta", so YMMV...
- Clint Olsen
Intel Hillsboro, OR
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From: Jon Harris <jharris@siroyan.com>
Hi, John,
I've found the Verilog 2000 support via the hdlin_enable_presto option is
excellent, especially if a lot of your logic structures are replicated. I
have had some code which is 10-20x as long as it needs to be to simply
because Verilog 1995 is so limiting and a lot of potential generate
constructs have to be 'unrolled'.
The question is - does anyone know of any simulators out there which support
Verilog 2000, as that's kind of important if you want to start coding in it!
- Jon Harris
Siroyan
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From: Brian Coffey <brian.coffey@analog.com>
Hi John,
PRESTO is Synopsys's new "HDL Compiler". I have used it and reported one or
two STARS against it. I think Synopsys hopes to introduce this in the next
release of Design Compiler as the default. I guess it is a "hidden switch"
in this release as it is in extended Beta. I actually found out about it on
a Synopsys Roadshow so it really wasn't hidden. Synopsys also have a new
Verilog gate netlist reader, which you can enable by setting
"set enable_verilog_netlist_reader true".
- Brian Coffey
Analog Devices Limerick, Ireland
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From: Menno Spijker <menno_spijker@Mitel.COM>
Hi John,
Presto is a new HDL Compiler. I had a problem with Design Compiler and here's
the message that I got back.
"Signal Declaration inside generate statement will be supported in the
next release of VHDL Compiler. The name of the new Compiler is Presto.
It will in 2000.11 release. VHDL Compiler (Presto) will not be enabled
by default. The manuals will include the variable setting to enable it.
Most VHDL-93 constructs will be covered as well."
Seems the switch is not active in the current release yet. But at least
people know about it now.
- Menno Spijker
Mitel Semiconductor Kanata, Canada
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From: Lars Bo Graversen <larsg@mips.com>
John,
Presto is the "new" HDL compiler which is included with DC release 2000.05.
It was mentioned in the Synthesis roadmap presentation at the recent DAC. I
have been playing around with it a little, but it keeps going "Fatal" on my
design. This seems to be related to the fact that we in general read in a
Verilog netlist containing some clock gating stuff (which is instantiated in
our RTL verilog) before reading in the RTL. This apparently does not (yet)
work with Presto.
"This is what is happening: The netlist reader is leaving the HDL Compiler
at some state, and is not resetting it before it's done. Reading in an
RTL file following it is causing Presto to fatal. There isn't any WA
for this, except to read the RTL before the netlist. This will be fixed
in the next release."
Is the answer I got from tech support on this issue.
- Lars Bo Graversen
MIPS Denmark
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